Vhdl 7系列收发器综合问题
我在项目中使用7系列GTX收发器向导时遇到一些合成问题。我设计了一个基本的定制协议和一个顶级包装器。在行为学中,一切都很好,但是在[15:0]中,当合成连接到Vhdl 7系列收发器综合问题,vhdl,fpga,vivado,Vhdl,Fpga,Vivado,我在项目中使用7系列GTX收发器向导时遇到一些合成问题。我设计了一个基本的定制协议和一个顶级包装器。在行为学中,一切都很好,但是在[15:0]中,当合成连接到gt0\u txdata\u的数据总线时,它没有正确地呈现,因此强制使用未知的“X”(在[1:0]中gt0\u txcharisk\u也会发生同样的情况)。我使用的是Vivado,编译器没有给我任何特别的警告。我还研究了gtwizard示例设计,我没有做任何与之不同的事情。 我正在开发我的Kintex-7FPGA项目 这里是范围和波动窗口:
gt0\u txdata\u的数据总线时,它没有正确地呈现,因此强制使用未知的“X”(在[1:0]
中gt0\u txcharisk\u也会发生同样的情况)。我使用的是Vivado,编译器没有给我任何特别的警告。我还研究了gtwizard示例设计,我没有做任何与之不同的事情。
我正在开发我的Kintex-7FPGA项目
这里是范围和波动窗口:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity protocol_frame_gen is
Port ( pfg_clk_in : in STD_LOGIC;
pfg_reset_in : in STD_LOGIC;
pfg_data_in : in STD_LOGIC_VECTOR (15 downto 0);
pfg_fifo_empty_in : in STD_LOGIC;
pfg_trasm_rqst_in : in STD_LOGIC;
pfg_fifo_rd_enable_out : out STD_LOGIC;
pfg_data_out : out STD_LOGIC_VECTOR (15 downto 0);
pfg_txcharisk: out STD_LOGIC_VECTOR (1 downto 0)
);
end protocol_frame_gen;
architecture Behavioral of protocol_frame_gen is
type state_type is ( idle, trasmission, dummy_state, end_trasmission);
signal state: state_type;
signal pfg_data_out_reg: STD_LOGIC_VECTOR (15 downto 0):= (others => '0');
signal mux_addr: integer range 0 to 3 := 0;
begin
pfg_data_out <= pfg_data_out_reg;
main: process(pfg_reset_in, pfg_clk_in)
begin
if pfg_reset_in='1' then
state <= idle;
mux_addr <= 0;
pfg_fifo_rd_enable_out <= '0';
elsif rising_edge(pfg_clk_in) then
case state is
when idle =>
if pfg_trasm_rqst_in='1' then
state <= trasmission;
end if;
when trasmission =>
if mux_addr<2 then
mux_addr <= mux_addr+1;
pfg_fifo_rd_enable_out <= '1';
else
null;
end if;
if pfg_fifo_empty_in='1' then
state <= end_trasmission;
pfg_fifo_rd_enable_out <= '0';
mux_addr <= 3;
end if;
when end_trasmission =>
mux_addr <= 0;
state <= idle;
when dummy_state =>
null;
end case;
end if;
end process main;
mux: process (pfg_clk_in)
begin
if rising_edge(pfg_clk_in) then
if mux_addr=0 then
pfg_data_out_reg <= "1111110111111101"; --idle character K29.7 1111110111111101
pfg_txcharisk <= "00";
elsif mux_addr=1 then
pfg_data_out_reg <= "0000000110111100"; --start of frame K28.5 1011110010111100
pfg_txcharisk <= "01";
elsif mux_addr=2 then
pfg_data_out_reg <= pfg_data_in; --valid data
pfg_txcharisk <= "00";
elsif mux_addr=3 then
pfg_data_out_reg <= "0001110000011100"; --end of frame K28.0
pfg_txcharisk <= "00";
end if;
end if;
end process mux;
end Behavioral;
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这是我的协议VHDL实体:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity protocol_frame_gen is
Port ( pfg_clk_in : in STD_LOGIC;
pfg_reset_in : in STD_LOGIC;
pfg_data_in : in STD_LOGIC_VECTOR (15 downto 0);
pfg_fifo_empty_in : in STD_LOGIC;
pfg_trasm_rqst_in : in STD_LOGIC;
pfg_fifo_rd_enable_out : out STD_LOGIC;
pfg_data_out : out STD_LOGIC_VECTOR (15 downto 0);
pfg_txcharisk: out STD_LOGIC_VECTOR (1 downto 0)
);
end protocol_frame_gen;
architecture Behavioral of protocol_frame_gen is
type state_type is ( idle, trasmission, dummy_state, end_trasmission);
signal state: state_type;
signal pfg_data_out_reg: STD_LOGIC_VECTOR (15 downto 0):= (others => '0');
signal mux_addr: integer range 0 to 3 := 0;
begin
pfg_data_out <= pfg_data_out_reg;
main: process(pfg_reset_in, pfg_clk_in)
begin
if pfg_reset_in='1' then
state <= idle;
mux_addr <= 0;
pfg_fifo_rd_enable_out <= '0';
elsif rising_edge(pfg_clk_in) then
case state is
when idle =>
if pfg_trasm_rqst_in='1' then
state <= trasmission;
end if;
when trasmission =>
if mux_addr<2 then
mux_addr <= mux_addr+1;
pfg_fifo_rd_enable_out <= '1';
else
null;
end if;
if pfg_fifo_empty_in='1' then
state <= end_trasmission;
pfg_fifo_rd_enable_out <= '0';
mux_addr <= 3;
end if;
when end_trasmission =>
mux_addr <= 0;
state <= idle;
when dummy_state =>
null;
end case;
end if;
end process main;
mux: process (pfg_clk_in)
begin
if rising_edge(pfg_clk_in) then
if mux_addr=0 then
pfg_data_out_reg <= "1111110111111101"; --idle character K29.7 1111110111111101
pfg_txcharisk <= "00";
elsif mux_addr=1 then
pfg_data_out_reg <= "0000000110111100"; --start of frame K28.5 1011110010111100
pfg_txcharisk <= "01";
elsif mux_addr=2 then
pfg_data_out_reg <= pfg_data_in; --valid data
pfg_txcharisk <= "00";
elsif mux_addr=3 then
pfg_data_out_reg <= "0001110000011100"; --end of frame K28.0
pfg_txcharisk <= "00";
end if;
end if;
end process mux;
end Behavioral;
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
--如果使用,请取消注释以下库声明
--具有有符号或无符号值的算术函数
--使用IEEE.NUMERIC_STD.ALL;
--如果正在实例化,请取消对以下库声明的注释
--此代码中的任何Xilinx叶细胞。
--UNISIM图书馆;
--使用UNISIM.VComponents.all;
实体协议_帧_gen为
端口(pfg_clk_in:标准逻辑中;
pfg_复位_输入:标准逻辑中;
pfg_数据_in:标准逻辑_向量(15向下至0);
pfg_fifo_empty_输入:标准逻辑中;
pfg_trasm_rqst_in:标准逻辑;
pfg_fifo_rd_enable_out:输出标准逻辑;
pfg_数据输出:输出标准逻辑向量(15向下至0);
pfg_txcharisk:输出标准逻辑向量(1到0)
);
结束协议_帧_gen;
协议_帧_gen的体系结构是
类型状态\类型为(空闲、传输、虚拟\状态、结束\传输);
信号状态:状态_型;
信号pfg_数据_out_reg:STD_逻辑_向量(15到0):=(其他=>'0');
信号mux_addr:整数范围0到3:=0;
开始
pfg_数据输出gt0_cpllreset_输入i,
gt0_drpaddr_in=>gt0_drpaddr_in_i,
gt0_drpdi_in=>gt0_drpdi_in_i,
gt0_drpdo_out=>gt0_drpdo_out_i,
gt0_drpen_in=>gt0_drpen_in_i,
gt0_drprdy_out=>gt0_drprdy_out_i,
gt0_drpwe_in=>gt0_drpwe_in_i,
gt0\u dmonitorout\u out=>gt0\u dmonitorout\u out\u i,
gt0_-eyescanreset_-in=>gt0_-eyescanreset_-in_i,
gt0_rxuserrdy_in=>gt0_rxuserrdy_in_i,
gt0_EyescandaError_out=>gt0_EyescandaError_out i,
gt0_目测仪_in=>gt0_目测仪_in_i,
gt0_rxdata_out=>gt0_rxdata_out_i,
gt0\u rxdisperr\u out=>gt0\u rxdisperr\u out\u i,
gt0_rxnotintable_out=>gt0_rxnotintable_out i,
gt0_gtxrxp_in=>gt0_gtxrxp_in_i,
gt0_gtxrxn_in=>gt0_gtxrxn_in_i,
gt0_rxdfelpmreset_in=>gt0_rxdfelpmreset_in_i,
gt0_rxmonitorout_out=>gt0_rxmonitorout_out i,
gt0_rxmonitorsel_in=>gt0_rxmonitorsel_in_i,
gt0_rxoutclkfabric_out=>gt0_rxoutclkfabric_out_i,
gt0_gtrxreset_in=>gt0_gtrxreset_in_i,
gt0_rxpmareset_in=>gt0_rxpmareset_in_i,
gt0_rxMComaalignen_in=>gt0_rxMComaalignen_in_i,
gt0_rxpcommaalignen_in=>gt0_rxpcommaalignen_in_i,
gt0_rxchariscomma_out=>gt0_rxchariscomma_out_i,
gt0_rxcharisk_out=>gt0_rxcharisk_out_i,
gt0_rxresetdone_out=>gt0_rxresetdone_out i,
gt0_gttxreset_in=>gt0_gttxreset_in_i,
gt0_txuserrdy_in=>gt0_txuserrdy_in_i,
gt0_txdata_in=>gt0_txdata_in_i,
gt0_gtxtxn_out=>gt0_gtxtxn_out_i,
gt0_gtxtxp_out=>gt0_gtxtxp_out_i,
gt0_txoutclkfabric_out=>gt0_txoutclkfabric_out_i,
gt0\U txoutclkpcs\U out=>gt0\U txoutclkpcs\U out\U i,
gt0_txcharisk_in=>gt0_txcharisk_in_i,
gt0_txresetdone_out=>gt0_txresetdone_out i,
GT0\u QPLLOUTCLK\u OUT=>GT0\u QPLLOUTCLK\u OUT\u i,
GT0qplootrefclk_OUT=>GT0qplootrefclk_OUT_i,
sysclk_in=>sysclk_in_i);
单元pfg:protocol_frame_gen端口图(pfg_clk_in=>pfg_clk_in_i,
pfg_reset_in=>pfg_reset_in_i,
pfg_数据_in=>pfg_数据_in_i,
pfg_fifo_empty_in=>pfg_fifo_empty_in_i,
pfg_trasm_rqst_in=>pfg_trasm_rqst_in_i,
pfg_fifo_rd_enable_out=>pfg_fifo_rd_enable_out i,
pfg_数据输出=>pfg_数据输出i,
pfg_txcharisk=>pfg_txcharisk_i);
单元pfc:协议\帧\检查端口映射(pfc\ U clk\ U in=>pfc\ U clk\ U in\ i,
pfc_reset_in=>pfc_reset_in_i,
pfc_数据_in=>pfc_数据_in_i,