Vhdl 为什么我的七段显示器只显示0'；s
我正在尝试为我的Nexys 4 DDR编写代码，以显示从键盘上选择的4位数字。Vhdl 为什么我的七段显示器只显示0'；s,vhdl,fpga,clock,keypad,seven-segment-display,Vhdl,Fpga,Clock,Keypad,Seven Segment Display,我正在尝试为我的Nexys 4 DDR编写代码，以显示从键盘上选择的4位数字。 它们输入JA端口，然后解码并显示在七段显示器上。按下新键后，数字应向左移动。 到目前为止，我的代码正在生成位流，但显示仅显示0，并且重置按钮似乎正在工作。我不确定这是时钟问题还是代码中的不一致 我已附上我的设计源和约束文件。 谢谢 你没有展示测试台。你写了吗？如果不是：总是，总是，当你的HDL代码超过几行代码时，总是做一个测试台。我没有，我对VHDL很陌生。创建测试台会很简单吗？其中一个case语句需要一个other
它们输入JA端口，然后解码并显示在七段显示器上。按下新键后，数字应向左移动。
到目前为止，我的代码正在生成位流，但显示仅显示0，并且重置按钮似乎正在工作。我不确定这是时钟问题还是代码中的不一致 我已附上我的设计源和约束文件。
谢谢
你没有展示测试台。你写了吗？如果不是：总是，总是，当你的HDL代码超过几行代码时，总是做一个测试台。我没有，我对VHDL很陌生。创建测试台会很简单吗？其中一个case语句需要一个others语句，而ja的inout模式端口会给您带来问题。在监视行信号（和去抖动）的同时，通过一次一个地下拉（低电平驱动）每个COL引脚来扫描键盘<代码>您需要ja（3到0）模拟可以通过传递每秒时钟的通用值并从中生成常量来代替用于sclk的位字符串文字来加快速度。一个100兆赫的时钟意味着大量的模拟器事件。@Oldfart同样适用于FPGA。花在测试台上的时间值得在硬件上进行双重调试。不幸的是，经理们并不总是看到这一点，他们很高兴发布有缺陷的产品，只是让客户发现缺陷并抱怨。我曾在FPGA团队工作，我们有一个验证团队在UVM中工作。软件发布后的bug返回量远远少于之前，大多数bug都是由于规范不完善或解释不当而产生的。您没有展示测试台。你写了吗？如果不是：总是，总是，当你的HDL代码超过几行代码时，总是做一个测试台。我没有，我对VHDL很陌生。创建测试台会很简单吗？其中一个case语句需要一个others语句，而ja的inout模式端口会给您带来问题。在监视行信号（和去抖动）的同时，通过一次一个地下拉（低电平驱动）每个COL引脚来扫描键盘<代码>您需要ja（3到0）模拟可以通过传递每秒时钟的通用值并从中生成常量来代替用于sclk的位字符串文字来加快速度。一个100兆赫的时钟意味着大量的模拟器事件。@Oldfart同样适用于FPGA。花在测试台上的时间值得在硬件上进行双重调试。不幸的是，经理们并不总是看到这一点，他们很高兴发布有缺陷的产品，只是让客户发现缺陷并抱怨。我曾在FPGA团队工作，我们有一个验证团队在UVM中工作。发布到软件后，bug返回的次数远远少于以前，而且大多数bug都是由于弱规范或解释不好的规范引起的。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;
entity PmodKYPD_Nexsy4 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
JA : inout STD_LOGIC_VECTOR (7 downto 0); -- PmodKYPD connected to Pmod JA
an : out STD_LOGIC_VECTOR (7 downto 0); -- Controls which position of the 8 seven segment displays to display
seg: out STD_LOGIC_VECTOR (6 downto 0)); -- digit to display on seven segment display
end PmodKYPD_Nexsy4;
architecture Behavioral of PmodKYPD_Nexsy4 is
component DisplayController is
Port ( DispVal : in STD_LOGIC_VECTOR (15 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0);
segOut : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal Decode: STD_LOGIC_VECTOR (3 downto 0);
signal RegLast : STD_LOGIC_VECTOR (15 downto 0);
signal refresh : STD_LOGIC_VECTOR (19 downto 0);
signal LEDAct : std_logic_vector(1 downto 0);
signal Row : STD_LOGIC_VECTOR (3 downto 0);
signal Col : STD_LOGIC_VECTOR (3 downto 0);
signal sclk :STD_LOGIC_VECTOR(19 downto 0);
signal DecodeOut : STD_LOGIC_VECTOR (3 downto 0);
signal Reg : unsigned(15 downto 0) := (others => '0');
begin
Row <= JA(7 downto 4);
Col <= JA(3 downto 0);
process(clk,reset)
begin
if(reset='1') then
refresh <= (others => '0');
elsif(rising_edge(clk)) then
refresh <= refresh + 1;
end if;
end process;
LEDAct <= refresh(19 downto 18);
process(clk)
begin
if clk'event and clk = '1' then
-- 1ms
if sclk = "00011000011010100000" then
--C1
Col<= "0111";
sclk <= sclk+1;
-- check row pins
elsif sclk = "00011000011010101000" then
--R1
if Row = "0111" then
DecodeOut <= "0001"; --1
--R2
elsif Row = "1011" then
DecodeOut <= "0100"; --4
--R3
elsif Row = "1101" then
DecodeOut <= "0111"; --7
--R4
elsif Row = "1110" then
DecodeOut <= "1111"; --F (mod from "0000"; --0)
end if;
sclk <= sclk+1;
-- 2ms
elsif sclk = "00110000110101000000" then
--C2
Col<= "1011";
sclk <= sclk+1;
-- check row pins
elsif sclk = "00110000110101001000" then
--R1
if Row = "0111" then
DecodeOut <= "0010"; --2
--R2
elsif Row = "1011" then
DecodeOut <= "0101"; --5
--R3
elsif Row = "1101" then
DecodeOut <= "1000"; --8
--R4
elsif Row = "1110" then
DecodeOut <= "0000"; --0 (mod from "1111"; --F)
end if;
sclk <= sclk+1;
--3ms
elsif sclk = "01001001001111100000" then
--C3
Col<= "1101";
sclk <= sclk+1;
-- check row pins
elsif sclk = "01001001001111101000" then
--R1
if Row = "0111" then
DecodeOut <= "0011"; --3
--R2
elsif Row = "1011" then
DecodeOut <= "0110"; --6
--R3
elsif Row = "1101" then
DecodeOut <= "1001"; --9
--R4
elsif Row = "1110" then
DecodeOut <= "1110"; --E
end if;
sclk <= sclk+1;
--4ms
elsif sclk = "01100001101010000000" then
--C4
Col<= "1110";
sclk <= sclk+1;
-- check row pins
elsif sclk = "01100001101010001000" then
--R1
if Row = "0111" then
DecodeOut <= "1010"; --A
--R2
elsif Row = "1011" then
DecodeOut <= "1011"; --B
--R3
elsif Row = "1101" then
DecodeOut <= "1100"; --C
--R4
elsif Row = "1110" then
DecodeOut <= "1101"; --D
end if;
sclk <= "00000000000000000000";
else
sclk <= sclk+1;
end if;
end if;
end process;
SHIFT_REG : process(clk)
variable tmp : unsigned(15 downto 0);
begin
if clk'event and clk = '1' then
tmp := Reg;
tmp := tmp sll 4;
tmp(3 downto 0) := unsigned(DecodeOut);
Reg <= tmp;
end if;
end process;
C0: DisplayController port map (DispVal=>STD_LOGIC_VECTOR(Reg), Selector=>LEDAct, anode=>an, segOut=>seg );
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DisplayController is
Port ( DispVal : in STD_LOGIC_VECTOR (15 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0);
segOut : out STD_LOGIC_VECTOR (6 downto 0));
end DisplayController;
architecture Behavioral of DisplayController is
begin
process(Selector)
begin
case Selector is
when "00" =>
anode <= "11110111";
-- activate LED1 and Deactivate LED2, LED3, LED4
-- the first hex digit of the 16-bit number
case DispVal(15 downto 12) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
when "01" =>
anode <= "11111011";
-- activate LED2 and Deactivate LED1, LED3, LED4
-- the second hex digit of the 16-bit number
case DispVal(11 downto 8) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
when "10" =>
anode <= "11111101";
-- activate LED3 and Deactivate LED2, LED1, LED4
-- the third hex digit of the 16-bit number
case DispVal(7 downto 4) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
when "11" =>
anode <= "11111110";
-- activate LED4 and Deactivate LED2, LED3, LED1
-- the fourth hex digit of the 16-bit number
case DispVal(3 downto 0) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
end case;
end process;
end Behavioral;
## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
##7 segment display
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { seg[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { seg[1] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { seg[2] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { seg[3] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { seg[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { seg[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { seg[6] }]; #IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
##Buttons
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L9P_T1_DQS_14 Sch=btnc
##Pmod Header JA
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10]