Compiler errors VHDL错误：Pack:2811-定向打包无法遵循用户设计
我正在从事一个VHDL项目，需要从开关获取一个4位的输入，并根据其他开关的值将其向右或向左移位一定数量的位—一个在向右/向左移位之间切换的按钮。然而，当我尝试在Xilinx ISE中实现我的代码时，我得到以下错误：错误：Pack:2811-定向打包无法遵守用户设计约束（LOC=T10），这要求将下面列出的符号组合打包到单个IOB组件中。我的问题是，是什么导致了这个错误，以及如何修复它 我的代码： BarrelShifter.vhdCompiler errors VHDL错误：Pack:2811-定向打包无法遵循用户设计,compiler-errors,vhdl,bit-shift,mux,Compiler Errors,Vhdl,Bit Shift,Mux,我正在从事一个VHDL项目，需要从开关获取一个4位的输入，并根据其他开关的值将其向右或向左移位一定数量的位—一个在向右/向左移位之间切换的按钮。然而，当我尝试在Xilinx ISE中实现我的代码时，我得到以下错误：错误：Pack:2811-定向打包无法遵守用户设计约束（LOC=T10），这要求将下面列出的符号组合打包到单个IOB组件中。我的问题是，是什么导致了这个错误，以及如何修复它 我的代码： BarrelShifter.vhd library IEEE; use IEEE.S
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BarrelShifter is
Port ( switchInput : inout STD_LOGIC_VECTOR (3 downto 0);
switchMode : inout STD_LOGIC_VECTOR (2 downto 0);
switchSelect : in STD_LOGIC_VECTOR (1 downto 0);
switchCopy : inout STD_LOGIC_VECTOR (3 downto 0);
buttonInput : in STD_LOGIC;
A,B,C,D,E,F,G,DP : out STD_LOGIC;
ax : out STD_LOGIC_VECTOR (3 downto 0);
display : inout STD_LOGIC_VECTOR (7 downto 0));
end BarrelShifter;
architecture Behavioral of BarrelShifter is
signal b0, b1, b2, b3, b4, b5, b6, b7: std_logic;
Component InputMux is
Port(bitInput : inout STD_LOGIC_VECTOR (3 downto 0);
shiftMode : inout STD_LOGIC_VECTOR (2 downto 0);
shiftSelect : in STD_LOGIC_VECTOR (1 downto 0);
buttonInput : in STD_LOGIC);
end component;
begin
switchMux : InputMux
port map(
bitInput => switchInput,
shiftMode => switchMode,
shiftSelect => switchSelect,
buttonInput => buttonInput
);
with switchInput select
display <= "11111100" when "0000", --0
"01100000" when "0001", --1
"11011010" when "0010", --2
"11110010" when "0011", --3
"01100110" when "0100", --4
"10110110" when "0101", --5
"10111110" when "0110", --6
"11100000" when "0111", --7
"11111110" when "1000", --8
"11100110" when "1001", --9
"11101110" when "1010", --A
"00111110" when "1011", --b
"10011100" when "1100", --C
"01111010" when "1101", --d
"10011110" when "1110", --E
"10001110" when "1111"; --F
b0 <= display(7);
b1 <= display(6);
b2 <= display(5);
b3 <= display(4);
b4 <= display(3);
b5 <= display(2);
b6 <= display(1);
b7 <= display(0);
a <= NOT b0;
b <= NOT b1;
c <= NOT b2;
d <= NOT b3;
e <= NOT b4;
f <= NOT b5;
g <= NOT b6;
dp <= NOT b7;
ax <= "0111";
end Behavioral;
IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
--如果使用，请取消注释以下库声明
--具有有符号或无符号值的算术函数
--使用IEEE.NUMERIC_STD.ALL；
--如果正在实例化，请取消对以下库声明的注释
--此代码中的任何Xilinx原语。
--UNISIM图书馆；
--使用UNISIM.VComponents.all；
实体桶移位器为
端口（开关输入：输入输出标准逻辑向量（3到0）；
开关模式：输入标准逻辑向量（2到0）；
开关选择：在标准逻辑向量中（1到0）；
开关拷贝：输入标准逻辑向量（3到0）；
按钮输入：在标准逻辑中；
A、 B、C、D、E、F、G、DP：输出标准逻辑；
ax：输出标准逻辑向量（3到0）；
显示：输入输出标准逻辑向量（7到0）；
端筒式换档器；
转筒器的结构是
信号b0、b1、b2、b3、b4、b5、b6、b7：标准逻辑；
组件InputMux是
端口（bitInput:inout标准逻辑向量（3到0）；
移位模式：输入输出标准逻辑向量（2到0）；
移位选择：在标准逻辑向量中（1到0）；
按钮输入：在标准逻辑中）；
端部元件；
开始
switchMux:InputMux
港口地图(
bitInput=>开关输入，
shiftMode=>switchMode，
shiftSelect=>switchSelect，
buttonInput=>buttonInput
);
使用开关输入选择
显示您已将输入引脚T10分配给两个不同的网络
NET buttonInput LOC = T10 ;
NET switchSelect<0> LOC = T10;
NET按钮输入LOC=T10；
净开关选择LOC=T10；
此错误表明工具不喜欢此操作。发生此错误的原因之一是您可能已将相同的Loc（位置）分配给两个或多个变量！
我也因此犯了同样的错误。
希望这能解决你的问题
## This file is a general .ucf for Nexys3 rev B board
## To use it in a project:
## - remove or comment the lines corresponding to unused pins
## - rename the used signals according to the project
## 7 segment display
NET ax<0> LOC = N16;
NET ax<1> LOC = N15;
NET ax<2> LOC = P18;
NET ax<3> LOC = P17;
NET A LOC = T17 ;#Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = CA
NET B LOC = T18 ;#Bank = 1, Pin name = IO_L51N_M1DQ13, Sch name = CB
NET C LOC = U17 ;#Bank = 1, Pin name = IO_L52P_M1DQ14, Sch name = CC
NET D LOC = U18 ;#Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = CD
NET E LOC = M14 ;#Bank = 1, Pin name = IO_L53P, Sch name = CE
NET F LOC = N14 ; #Bank = 1, Pin name = IO_L53N_VREF, Sch name = CF
NET G LOC = L14 ; #Bank = 1, Pin name = IO_L61P, Sch name = CG
NET DP LOC = M13 ; #Bank = 1, Pin name = IO_L61N, Sch name = DP
NET buttonInput LOC = T10 ;
#NET "an<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50N_M1UDQSN, Sch name = AN0
#NET "an<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50P_M1UDQS, Sch name = AN1
#NET "an<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49N_M1DQ11, Sch name = AN2
#NET "an<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49P_M1DQ10, Sch name = AN3
## Leds
#NET "Led<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = LD0
#NET "Led<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = LD1
#NET "Led<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5P, Sch name = LD2
#NET "Led<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5N, Sch name = LD3
#NET "Led<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15P, Sch name = LD4
#NET "Led<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15N, Sch name = LD5
#NET "Led<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16P, Sch name = LD6
#NET "Led<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16N_VREF, Sch name = LD7
## Switches
#NET "sw<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = SW0
#NET "sw<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = SW1
#NET "sw<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = SW2
#NET "sw<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40P, Sch name = SW3
#NET "sw<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40N, Sch name = SW4
#NET "sw<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41P, Sch name = SW5
#NET "sw<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41N_VREF, Sch name = SW6
#NET "sw<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #Bank = MISC, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7
NET switchInput<3> LOC = T5;
NET switchInput<2> LOC = V8;
NET switchInput<1> LOC = U8;
NET switchInput<0> LOC = N8;
NET switchSelect<0> LOC = T10;
NET switchSelect<1> LOC = T9;
## Buttons
#NET "btn<0>" LOC = "B8" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L33P, Sch name = BTNS
#NET "btn<1>" LOC = "A8" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L33N, Sch name = BTNU
#NET "btn<2>" LOC = "C4" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L1N_VREF, Sch name = BTNL
#NET "btn<3>" LOC = "C9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = BTND
#NET "btn<4>" LOC = "D9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = BTNR
NET buttonInput LOC = T10 ;
NET switchSelect<0> LOC = T10;