Vhdl 进程语句中的（并发）信号分配是连续的还是并发的？

据我所知，进程中的所有语句都是按顺序执行的。那么并发信号分配（信号分配（顺序信号分配）会发生什么情况呢(

signal a : std_logic := '1'; --initial value is 1

process(clk)
  variable b : std_logic;
begin
  --note that the variable assignment operator, :=, can only be used to assign the value of variables, never signals
  --Likewise, the signal assignment operator, <=, can only be used to assign the value of signals.
  if (clk'event and clk='1') then
    b := '0' --b is made '0' right now.
    a <= b; --a will be made the current value of b ('0') at time t+delta
    a <= '0'; --a will be made '0' at time t+delta (overwrites previous event scheduling for a)
    b := '1' --b will be made '1' right now. Any future uses of b will be equivalent to replacing b with '1'
    a <= b; --a will be made the current value of b ('1') at time t+delta
    a <= not(a); --at time t+delta, a will be inverted. None of the previous assignments to a matter, their scheduled event have been overwritten
    --after the end of the process, b does not matter because it cannot be used outside of the process, and gets reset at the start of the process
  end if;
end process;