If statement VHDL-物理设计规则：367

当我尝试从我的VHDL代码合成、实现和生成程序文件时，我收到了警告

当我尝试合成时，我得到了这个错误

WARNING:Xst:647 - Input <BTN_3> is never used. 
    This port will be preserved and left unconnected if it 
    belongs to a top-level block or it belongs to a sub-block and 
    the hierarchy of this sub-block is preserved.

WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. 
    The signal does not drive any load pins in the design.

---

您发布的代码可能无法说明全部情况。通常有一个接口（用户约束，谢谢Bob）文件，用于定义引脚边缘输入和输出到您定义的FPGA内部电路的端口。我没有看到

其次，我在代码中还看到，有两个不同的电路驱动每个输出LED

您有一个if语句，用于检查BTN_3是否为1，这将驱动所有LED为0，然后是一组if语句，用于检查每个“开关_X”的输入状态，每个开关分别驱动一个0或一个LED。这实际上是非法的。您只能有一个电路驱动任何输出端口

您应该做的是按如下方式编写此电路：

architecture Behavioral of Switch_led is
begin
  Process(Switch_0, Switch_1, Switch_2, Switch_3, Switch_4, Switch_5, Switch_6 , Switch_7, BTN_3)
  begin

    if BTN_3 = '1' then 
      Led_0 <= '0';
      Led_1 <= '0';
      Led_2 <= '0';
      Led_3 <= '0';
      Led_4 <= '0';
      Led_5 <= '0';
      Led_6 <= '0';
      Led_7 <= '0';
    else

      if Switch_0 = '1' then
        Led_0 <= '1';
      else
        Led_0 <= '0';
      end if;

      if Switch_1 = '1' then
        Led_1 <= '1';
      else
        Led_1 <= '0';
      end if;

      if Switch_2 = '1' then
        Led_2 <= '1';
      else
        Led_2 <= '0';
      end if;

      if Switch_3 = '1' then
        Led_3 <= '1';
      else
        Led_3 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_5 = '1' then
        Led_5 <= '1';
      else
        Led_5 <= '0';
      end if;

      if Switch_6 = '1' then
        Led_6 <= '1';
      else
        Led_6 <= '0';
      end if;

      if Switch_7 = '1' then
        Led_7 <= '1';
      else
        Led_7 <= '0';
      end if;

    end if;

  end process;
end Behavioral;

开关led的架构行为为
开始
过程（开关0、开关1、开关2、开关3、开关4、开关5、开关6、开关7、BTN\U 3）
开始
如果BTN_3='1'，则
Led_0要查看的代码在哪里？？？我想这意味着你正在使用一个芯片边缘输入缓冲区，正如你在接口文件中定义的那样，但在某个地方你没有将该引脚连接到任何电路，这就是警告647告诉你的。@BobBurt-是的，这就是LOL。在我的回答编辑中感谢你@博伯特-你改变了什么，现在它正在工作？你把密码改成我的答案了吗？如果是这样的话，那也是有道理的，因为你基本上是在用多个内部驱动电路驱动一个输出管脚。我想我刚才把我的else语句改成了你的，这也比我的更有意义。我注意到，我可以用矢量来代替计算is开关和LED。。相反，我本可以写的所有if语句
NET "Switch_0" LOC = "G18";
    NET "Switch_1" LOC = "H18";
    NET "Switch_2" LOC = "K18";
    NET "Switch_3" LOC = "K17";
    NET "Switch_4" LOC = "L14";
    NET "Switch_5" LOC = "L13";
    NET "Switch_6" LOC = "N17";
    NET "Switch_7" LOC = "R17";
    NET "LED_0" LOC = "J14";
    NET "LED_1" LOC = "J15";
    NET "LED_2" LOC = "K15";
    NET "LED_3" LOC = "K14";
    NET "LED_4" LOC = "E17";
    NET "LED_5" LOC = "P15";
    NET "LED_6" LOC = "F4";
    NET "LED_7" LOC = "R4";
    NET "BTN_3" LOC = "H13";

architecture Behavioral of Switch_led is
begin
  Process(Switch_0, Switch_1, Switch_2, Switch_3, Switch_4, Switch_5, Switch_6 , Switch_7, BTN_3)
  begin

    if BTN_3 = '1' then 
      Led_0 <= '0';
      Led_1 <= '0';
      Led_2 <= '0';
      Led_3 <= '0';
      Led_4 <= '0';
      Led_5 <= '0';
      Led_6 <= '0';
      Led_7 <= '0';
    else

      if Switch_0 = '1' then
        Led_0 <= '1';
      else
        Led_0 <= '0';
      end if;

      if Switch_1 = '1' then
        Led_1 <= '1';
      else
        Led_1 <= '0';
      end if;

      if Switch_2 = '1' then
        Led_2 <= '1';
      else
        Led_2 <= '0';
      end if;

      if Switch_3 = '1' then
        Led_3 <= '1';
      else
        Led_3 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_5 = '1' then
        Led_5 <= '1';
      else
        Led_5 <= '0';
      end if;

      if Switch_6 = '1' then
        Led_6 <= '1';
      else
        Led_6 <= '0';
      end if;

      if Switch_7 = '1' then
        Led_7 <= '1';
      else
        Led_7 <= '0';
      end if;

    end if;

  end process;
end Behavioral;