Linux #设备树覆盖范围属性中的地址单元格和#大小单元格字段

我正在尝试将一个文件加载到stratix10 FPGA中，并使用运行linux的嵌入式硬件处理器ARM映射FPGA总线

（Linux 5.4.23-03466-gcc83036e6a78#1 SMP抢占，星期三8月5日10:15:00 CEST 2020 aarch64 GNU/Linux）。

这是通过设备树覆盖完成的

主设备树包含：（其中[…]表示删除的部分-希望-无中断）

请注意，在父节点（

/soc

）和子节点（

/soc/base\u fpga\u region

）中，字段

#address cells

和

#size cells

都设置为

。 因此，我最初尝试的设备树覆盖如下所示：

/dts-v1/;
/plugin/;
/ {
        fragment@1 {
                target-path = "/soc/base_fpga_region";
                __overlay__ {
                        firmware-name = "fpga_image.rbf";
                        config-complete-timeout-us = <3000000>;
                        #address-cells = <1>;                           /* address in the child (fpga region) space are given as 1 U32 values */
                        #size-cells = <1>;                              /* sizes   in the child (fpga region) space are given as 1 U32 values */
                                                                        /* mapping from ARM address to FPGA addresses: */
                                                                        /* see https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html */
                        ranges = <0x00000000 0x80000000 0x40000000>,    /* hps to FPGA mapping: address 0 of the child bus mapps to address 80000000 in the parent space: length 0x40000 */
                                 <0x00000000 0xf9000000 0x00200000>;    /* lightweight hps to FPGA mapping: 0 maps to parent f9000000. length 1000 */
                };
        };
};

好的。。。毕竟，在编译我的覆盖时，编译器可能不太了解父节点

/soc

，而是为

#地址单元格

和

#大小单元格

采用默认值。。。 因此，我在覆盖图中添加了一个小提示，如下所示：

dts-v1/;
/plugin/;
/ {
        fragment@0 {
                target-path = "/soc";
                __overlay__ {
                        #address-cells = <1>;                           /* */
                        #size-cells = <1>;                              /* */
                };
        };

        fragment@1 {
                target-path = "/soc/base_fpga_region";
                __overlay__ {
                        firmware-name = "fpga_image.rbf";
                        config-complete-timeout-us = <3000000>;
                        #address-cells = <1>;                           /* address in the child (fpga region) space are given as 1 U32 values */
                        #size-cells = <1>;                              /* sizes   in the child (fpga region) space are given as 1 U32 values */
                                                                        /* mapping from ARM address to FPGA addresses: */
                                                                        /* see https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html */
                        ranges = <0x00000000 0x80000000 0x40000000>,    /* hps to FPGA mapping: address 0 of the child bus mapps to address 80000000 in the parent space: length 0x40000 */
                                 <0x00000000 0xf9000000 0x00200000>;    /* lightweight hps to FPGA mapping: 0 maps to parent f9000000. length 1000 */
                };
        };
};

这让我有点困惑：父

/soc

节点的

#地址单元

现在已明确指定（两次：一次在原始设备树中，一次在覆盖中）

发生了什么事？我做错了什么

在绝望中，我也尝试了（注意范围规范中父地址的额外零）：

但是，当我应用覆盖并尝试访问映射区域中的某些内容（例如，轻型总线的地址0xF9000000处）时，会导致

总线错误

。。。这可能告诉我，即使这样做也没有如我所愿

设备树规范说明：

子总线地址是子总线内的物理地址 地址空间。表示地址的单元数为总线 依赖，可从该节点的#地址单元确定 （显示“范围”属性的节点）

父总线地址 是父总线地址空间中的物理地址。号码 表示父地址的单元数取决于总线，可以 根据定义的节点的#address Cells属性确定 父级的地址空间

长度指定范围的大小 在孩子的地址空间中。要表示的单元格数 大小可以通过此节点（中的节点）的#大小单元格确定 显示的范围属性）

从这一点上，我不明白为什么我的第一次，或者至少第二次尝试失败了。 当涉及到第三次绝望的尝试时，我不确定能做些什么，但我很感谢大家的评论。

---

感谢

大小单元格不必从父级继承，它取决于地址的数量：您有两个地址，因此应该是#大小单元格=；当然？编译器说在某个地方有一个，但我不知道这是从哪里来的。。。我的dts/dtsi文件中到处都有，不是吗？其中有ranges=；这就是我的意思，你自己引用它：长度指定子地址空间中范围的大小#大小单元格=；但这些事情有时非常棘手；）

/dts-v1/;
/plugin/;
/ {
        fragment@1 {
                target-path = "/soc/base_fpga_region";
                __overlay__ {
                        firmware-name = "fpga_image.rbf";
                        config-complete-timeout-us = <3000000>;
                        #address-cells = <1>;                           /* address in the child (fpga region) space are given as 1 U32 values */
                        #size-cells = <1>;                              /* sizes   in the child (fpga region) space are given as 1 U32 values */
                                                                        /* mapping from ARM address to FPGA addresses: */
                                                                        /* see https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html */
                        ranges = <0x00000000 0x80000000 0x40000000>,    /* hps to FPGA mapping: address 0 of the child bus mapps to address 80000000 in the parent space: length 0x40000 */
                                 <0x00000000 0xf9000000 0x00200000>;    /* lightweight hps to FPGA mapping: 0 maps to parent f9000000. length 1000 */
                };
        };
};

arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:13.4-14.41: Warning (ranges_format): /fragment@1/__overlay__:ranges: "ranges" property has invalid length (24 bytes) (parent #address-cells == 2, child #address-cells == 1, #size-cells == 1)
arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:6.15-15.5: Warning (avoid_default_addr_size): /fragment@1/__overlay__: Relying on default #address-cells value
arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:6.15-15.5: Warning (avoid_default_addr_size): /fragment@1/__overlay__: Relying on default #size-cells value

dts-v1/;
/plugin/;
/ {
        fragment@0 {
                target-path = "/soc";
                __overlay__ {
                        #address-cells = <1>;                           /* */
                        #size-cells = <1>;                              /* */
                };
        };

        fragment@1 {
                target-path = "/soc/base_fpga_region";
                __overlay__ {
                        firmware-name = "fpga_image.rbf";
                        config-complete-timeout-us = <3000000>;
                        #address-cells = <1>;                           /* address in the child (fpga region) space are given as 1 U32 values */
                        #size-cells = <1>;                              /* sizes   in the child (fpga region) space are given as 1 U32 values */
                                                                        /* mapping from ARM address to FPGA addresses: */
                                                                        /* see https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html */
                        ranges = <0x00000000 0x80000000 0x40000000>,    /* hps to FPGA mapping: address 0 of the child bus mapps to address 80000000 in the parent space: length 0x40000 */
                                 <0x00000000 0xf9000000 0x00200000>;    /* lightweight hps to FPGA mapping: 0 maps to parent f9000000. length 1000 */
                };
        };
};

arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:21.4-22.41: Warning (ranges_format): /fragment@1/__overlay__:ranges: "ranges" property has invalid length (24 bytes) (parent #address-cells == 2, child #address-cells == 1, #size-cells == 1)
arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:14.15-23.5: Warning (avoid_default_addr_size): /fragment@1/__overlay__: Relying on default #address-cells value
arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:14.15-23.5: Warning (avoid_default_addr_size): /fragment@1/__overlay__: Relying on default #size-cells value

/dts-v1/;
/plugin/;
/ {
        fragment@1 {
                target-path = "/soc/base_fpga_region";
                __overlay__ {
                        firmware-name = "fpga_image.rbf";
                        config-complete-timeout-us = <3000000>;
                        #address-cells = <1>;                           /* address in the child (fpga region) space are given as 1 U32 values */
                        #size-cells = <1>;                              /* sizes   in the child (fpga region) space are given as 1 U32 values */
                                                                        /* mapping from ARM address to FPGA addresses: */
                                                                        /* see https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html */
                        ranges = <0x00000000 0 0x80000000 0x40000000>,  /* hps to FPGA mapping: address 0 of the child bus mapps to address 80000000 in the parent space: length 0x40000 */
                                 <0x00000000 0 0xf9000000 0x00200000>;  /* lightweight hps to FPGA mapping: 0 maps to parent f9000000. length 1000 */
                };
        };
};

arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:6.15-15.5: Warning (avoid_default_addr_size): /fragment@1/__overlay__: Relying on default #address-cells value
arch/arm64/boot/dts/altera/socfpga_stratix10_ovl_load.dts:6.15-15.5: Warning (avoid_default_addr_size): /fragment@1/__overlay__: Relying on default #size-cells value