Process 设计FSM'；在VHDL中使用带端口映射的去Bounce
我用VHDL制作了FSM，现在我想使用端口映射的去盎司代码。 虽然我在联想方面有困难。事实上，我想在驱动FSM的信号中插入Process 设计FSM'；在VHDL中使用带端口映射的去Bounce,process,vhdl,clock,fsm,Process,Vhdl,Clock,Fsm,我用VHDL制作了FSM，现在我想使用端口映射的去盎司代码。 虽然我在联想方面有困难。事实上，我想在驱动FSM的信号中插入debouncebutton组件 entity myFSM is Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; IN0 : in STD_LOGIC; IN1 : in STD_LOGIC; IN2 : in STD_LOG
debouncebuttonentity myFSM is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN0 : in STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end myFSM;
architecture Behavioral of myFSM is
type state is (A, B, C);
signal currentS, nextS: state;
component debouncebutton
Port ( clk : in std_logic; -- connect it to the Clock of the board
rst : in std_logic; -- connect it to the Reset Button of the board
input : in std_logic; -- connect it to the Push Button of the board
output : out std_logic -- connect it to your circuit
);
end component;
begin
myFSM_comb: process (currentS, IN0, IN1, IN2)
begin
case currentS is
when A => LED <= "11111111";
if IN0 = '1' then nextS<=B;
elsif IN1 = '1' then nextS<=C;
else nextS<=A;
end if;
when B => LED <= "11000011";
if IN0 = '1' then nextS<=C;
elsif IN1 = '1' then nextS<=A;
else nextS<=B;
end if;
when C => LED <= "00111100";
if IN0 = '1' then nextS<=A;
elsif IN1 = '1' then nextS<=B;
else nextS<=C;
end if;
end case;
end process;
myFSM_synch: process(CLK,RST)
begin
if (RST='1') then currentS<=A;
elsif (rising_edge(CLK)) then currentS<= nextS;
end if;
end process ;
begin
db0 : debounce
port map
(
clk => CLK,
rst => RST,
input => IN0,
output
end Behavioral;
实体myFSM是
端口（时钟：在标准逻辑中；
RST：标准逻辑中；
IN0:in标准逻辑；
IN1：标准逻辑；
IN2:in标准逻辑；
LED：输出标准逻辑向量（7到0）；
结束多年筹资机制；
myFSM的架构是
类型状态为（A、B、C）；
信号电流，nextS：状态；
组件去抖动按钮
端口（时钟：在std_逻辑中；--将其连接到板的时钟
rst：在std_逻辑中；--将其连接到板的复位按钮
输入：在std_逻辑中；--将其连接到板的按钮
输出：输出标准逻辑——将其连接到电路
);
端部元件；
开始
myFSM_梳：过程（电流，IN0，IN1，IN2）
开始
案例电流为
当A=>LED我通过在端口声明中将IN0重命名为INP0来标记代码时，在体系结构中声明了一个名为INO的信号，以防止每次出现名称时都更改，删除了一个无关的begin
，并将实例化组件从debounce
重命名为debouncebutton
，以匹配组件声明：
library ieee;
use ieee.std_logic_1164.all;
entity myFSM is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
INP0 : in STD_LOGIC; -- name changed
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end myFSM;
architecture Behavioral of myFSM is
type state is (A, B, C);
signal currentS, nextS: state;
component debouncebutton
Port ( clk : in std_logic; -- connect it to the Clock of the board
rst : in std_logic; -- connect it to the Reset Button of the board
input : in std_logic; -- connect it to the Push Button of the board
output : out std_logic -- connect it to your circuit
);
end component;
signal IN0: std_logic; --- added
begin
myFSM_comb: process (currentS, IN0, IN1, IN2)
begin
case currentS is
when A => LED <= "11111111";
if IN0 = '1' then nextS<=B;
elsif IN1 = '1' then nextS<=C;
else nextS<=A;
end if;
when B => LED <= "11000011";
if IN0 = '1' then nextS<=C;
elsif IN1 = '1' then nextS<=A;
else nextS<=B;
end if;
when C => LED <= "00111100";
if IN0 = '1' then nextS<=A;
elsif IN1 = '1' then nextS<=B;
else nextS<=C;
end if;
end case;
end process;
myFSM_synch: process(CLK,RST)
begin
if (RST='1') then currentS<=A;
elsif (rising_edge(CLK)) then currentS<= nextS;
end if;
end process ;
-- begin -- syntax error you have a begin before process myFSB_comb
db0 : debouncebutton --- was debounce, needs to match component declaration
port map (
clk => CLK,
rst => RST,
input => INP0, -- renamed input port
output=> IN0 -- newly declared signal INO
);
end Behavioral;
ieee库；
使用ieee.std_logic_1164.all；
实体myFSM是
端口（时钟：在标准逻辑中；
RST：标准逻辑中；
INP0:在标准逻辑中；--名称已更改
IN1：标准逻辑；
IN2:in标准逻辑；
LED：输出标准逻辑向量（7到0）；
结束多年筹资机制；
myFSM的架构是
类型状态为（A、B、C）；
信号电流，nextS：状态；
组件去抖动按钮
端口（时钟：在std_逻辑中；--将其连接到板的时钟
rst：在std_逻辑中；--将其连接到板的复位按钮
输入：在std_逻辑中；--将其连接到板的按钮
输出：输出标准逻辑——将其连接到电路
);
端部元件；
信号输入0:std_逻辑；——补充
开始
myFSM_梳：过程（电流，IN0，IN1，IN2）
开始
案例电流为
当A=>LED我通过在端口声明中将IN0重命名为INP0来标记代码时，在体系结构中声明了一个名为INO的信号，以防止每次出现名称时都更改，删除了一个无关的begin
，并将实例化组件从debounce
重命名为debouncebutton
，以匹配组件声明：
library ieee;
use ieee.std_logic_1164.all;
entity myFSM is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
INP0 : in STD_LOGIC; -- name changed
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end myFSM;
architecture Behavioral of myFSM is
type state is (A, B, C);
signal currentS, nextS: state;
component debouncebutton
Port ( clk : in std_logic; -- connect it to the Clock of the board
rst : in std_logic; -- connect it to the Reset Button of the board
input : in std_logic; -- connect it to the Push Button of the board
output : out std_logic -- connect it to your circuit
);
end component;
signal IN0: std_logic; --- added
begin
myFSM_comb: process (currentS, IN0, IN1, IN2)
begin
case currentS is
when A => LED <= "11111111";
if IN0 = '1' then nextS<=B;
elsif IN1 = '1' then nextS<=C;
else nextS<=A;
end if;
when B => LED <= "11000011";
if IN0 = '1' then nextS<=C;
elsif IN1 = '1' then nextS<=A;
else nextS<=B;
end if;
when C => LED <= "00111100";
if IN0 = '1' then nextS<=A;
elsif IN1 = '1' then nextS<=B;
else nextS<=C;
end if;
end case;
end process;
myFSM_synch: process(CLK,RST)
begin
if (RST='1') then currentS<=A;
elsif (rising_edge(CLK)) then currentS<= nextS;
end if;
end process ;
-- begin -- syntax error you have a begin before process myFSB_comb
db0 : debouncebutton --- was debounce, needs to match component declaration
port map (
clk => CLK,
rst => RST,
input => INP0, -- renamed input port
output=> IN0 -- newly declared signal INO
);
end Behavioral;
ieee库；
使用ieee.std_logic_1164.all；
实体myFSM是
端口（时钟：在标准逻辑中；
RST：标准逻辑中；
INP0:在标准逻辑中；--名称已更改
IN1：标准逻辑；
IN2:in标准逻辑；
LED：输出标准逻辑向量（7到0）；
结束多年筹资机制；
myFSM的架构是
类型状态为（A、B、C）；
信号电流，nextS：状态；
组件去抖动按钮
端口（时钟：在std_逻辑中；--将其连接到板的时钟
rst：在std_逻辑中；--将其连接到板的复位按钮
输入：在std_逻辑中；--将其连接到板的按钮
输出：输出标准逻辑——将其连接到电路
);
端部元件；
信号输入0:std_逻辑；——补充
开始
myFSM_梳：过程（电流，IN0，IN1，IN2）
开始
案例电流为
当A=>发光二极管