Time 时间代码可以编译,但不会';t工作VHDL模型
因此,本实验室的重点是在ModelSim中模拟模块代码,以显示计时器使用测试台工作(我无法更改)。当我进行模拟时,只有时钟波形发生了变化,我所有的十六进制显示在任何时候都是0b1000000。有人能帮我找出计时器为什么不运行吗 代码:Time 时间代码可以编译,但不会';t工作VHDL模型,time,vhdl,clock,modelsim,Time,Vhdl,Clock,Modelsim,因此,本实验室的重点是在ModelSim中模拟模块代码,以显示计时器使用测试台工作(我无法更改)。当我进行模拟时,只有时钟波形发生了变化,我所有的十六进制显示在任何时候都是0b1000000。有人能帮我找出计时器为什么不运行吗 代码: ieee库; 使用ieee.std_logic_1164.all; 使用ieee.std_logic_arith.all; 使用ieee.numeric_std.all; 使用ieee.std_logic_unsigned.all; 实体PRELAB7是 端口(时
ieee库;
使用ieee.std_logic_1164.all;
使用ieee.std_logic_arith.all;
使用ieee.numeric_std.all;
使用ieee.std_logic_unsigned.all;
实体PRELAB7是
端口(时钟、负载、复位):在标准逻辑中;
sw:标准逻辑向量(15到0);
--对于设置的hr min sec
hex2:输出标准逻辑向量(6到0);
hex4:输出标准逻辑向量(6到0);
hex6:输出标准逻辑向量(6到0);
hex3:输出标准逻辑向量(6到0);
hex5:输出标准逻辑向量(6到0);
hex7:输出标准逻辑向量(6到0)
);
结束前AB7;
PRELAB7的架构是
信号秒、分钟、小时:标准逻辑向量(6到0);
信号整数计数:标准逻辑矢量(27到0);
常量最大值:标准逻辑向量(27到0):=x“2FAF080”;
信号定时器_标志:标准_逻辑;
信号温度秒、温度分钟、温度小时:标准逻辑向量(6到0):=“0000000”;
常数零:标准逻辑向量(6到0):=“1000000”--0
常数1:STD_逻辑_向量(6到0):=“1111001”--1.
常数二:标准逻辑向量(6到0):=“0100100”--2.
常数三:标准逻辑向量(6到0):=“011000”--3.
常数四:标准逻辑向量(6到0):=“0011001”--4.
常数五:标准逻辑向量(6到0):=“0010”--5.
常数六:标准逻辑向量(6到0):=“0000010”--6.
常数七:标准逻辑向量(6到0):=“1111000”--7.
常数8:STD_逻辑_向量(6到0):=“0000000”--8.
常数九:标准逻辑向量(6到0):=“0010000”--9
开始
定时器:进程(时钟、复位)
开始
如果(reset_n='0'),则
整数计数“0”);
elsif(上升沿(clk))然后
如果(整数计数=最大值),则
整数计数“0”);
计时器标志计数器卡住的一个原因是复位信号是reset\n
,其中
\n
通常表示复位在低电平(0)时处于活动状态,即
本设计中的情况也是如此,从试验台和波形中可以看出
但是,PRELAB7
模块使用复位,如同高电平激活一样,如中所示
此代码和其他代码部分:
...
seconds:PROCESS(reset_n,sec,clk,load_n)
BEGIN
if (reset_n = '1' OR sec > 59 OR load_n = '1') then
sec <= "0000000";
else
if(rising_edge(clk)) then
sec <= sec + 1;
...
原因是,秒
计数器中不同位的更新可能会略微倾斜
在硬件中,由于内部定时,因此在更新过程中,sec
可能显示为:
55:0b110111(沉淀后的最终值)
63:0b111111(位3在位2:0到达“0”之前到达“1”的中间值)
56:0b111000(沉淀后的最终值)
因此表达式的sec>59
部分可能在意外时间为真,并且
根据内部定时,这可能导致(部分)异步复位
如果在硬件中实现,那么这些问题很难发现,因为它们不会
在模拟中显示
--*****************************************************************************
--*************************** VHDL Source Code ******************************
--********* Copyright 2010, Rochester Institute of Technology ***************
--*****************************************************************************
--
-- DESIGNER NAME: Jeanne Christman
--
-- LAB NAME: VHDL Timers and Counter
--
-- FILE NAME: TOD_tb.vhd
--
-------------------------------------------------------------------------------
--
-- DESCRIPTION
--
-- This test bench will provide input to test the implemention of the
-- circuit on the DE2 board that acts as a time-of-day clock. It displays
-- the hour (from 0 to 23) on the 7-segment displays HEX7-6, the minute
-- (from 0 to 60) on HEX5-4 and the second (from 0 to 60) on HEX3-2.
-- The contents of the value displayed on the 7-segment displays must be
-- manually verfied.
--
-------------------------------------------------------------------------------
--
-- REVISION HISTORY
--
-- _______________________________________________________________________
-- | DATE | USER | Ver | Description |
-- |==========+======+=====+================================================
-- | | | |
-- | 10/16/13 | JWC | 1.0 | Created
-- | | | |
--
--*****************************************************************************
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TOD_tb IS
END TOD_tb;
ARCHITECTURE test OF TOD_tb IS
-- Component Declaration for the Unit Under Test (UUT)
-- if you use a package with the component defined then you do not need this
COMPONENT PRELAB7
PORT (
clk : IN std_logic;
reset_n : IN std_logic;
load_n : IN std_logic;
SW : IN std_logic_vector(15 DOWNTO 0);
--
hex2 : OUT std_logic_vector(6 DOWNTO 0);
hex3 : OUT std_logic_vector(6 DOWNTO 0);
hex4 : OUT std_logic_vector(6 DOWNTO 0);
hex5 : OUT std_logic_vector(6 DOWNTO 0);
hex6 : OUT std_logic_vector(6 DOWNTO 0);
hex7 : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
-- define signals for component ports
SIGNAL clock_50 : std_logic := '0';
SIGNAL sys_reset_n : std_logic := '0';
SIGNAL load_enable_n : std_logic := '0';
SIGNAL bcd_load_time : std_logic_vector(15 DOWNTO 0) := x"0000";
--
-- Outputs
SIGNAL hex2 : std_logic_vector(6 DOWNTO 0);
SIGNAL hex3 : std_logic_vector(6 DOWNTO 0);
SIGNAL hex4 : std_logic_vector(6 DOWNTO 0);
SIGNAL hex5 : std_logic_vector(6 DOWNTO 0);
SIGNAL hex6 : std_logic_vector(6 DOWNTO 0);
SIGNAL hex7 : std_logic_vector(6 DOWNTO 0);
-- signals for test bench control
SIGNAL sim_done : boolean := false;
SIGNAL PERIOD_c : time := 20 ns; -- 50MHz
BEGIN -- test
-- component instantiation
UUT : PRELAB7
PORT MAP (
clk => clock_50,
reset_n => sys_reset_n,
load_n => load_enable_n,
SW => bcd_load_time,
--
hex2 => hex2,
hex3 => hex3,
hex4 => hex4,
hex5 => hex5,
hex6 => hex6,
hex7 => hex7
);
-- This creates an clock_50 that will shut off at the end of the Simulation
-- this makes a clock_50 that you can shut off when you are done.
clock_50 <= NOT clock_50 AFTER PERIOD_C/2 WHEN (NOT sim_done) ELSE '0';
---------------------------------------------------------------------------
-- NAME: Stimulus
--
-- DESCRIPTION:
-- This process will apply stimulus to the UUT.
---------------------------------------------------------------------------
stimulus : PROCESS
BEGIN
-- de-assert all inputs except the reset which is asserted
sys_reset_n <= '0';
load_enable_n <= '1';
bcd_load_time <= x"0000";
WAIT FOR 5 ns;
-- now lets sync the stimulus to the clock_50
-- move stimulus 1ns after clock edge
WAIT UNTIL clock_50 = '1';
WAIT FOR 1 ns;
-- de-assert reset and let run for 4 seconds
sys_reset_n <= '1';
WAIT FOR 20*PERIOD_C; -- adjust this time to lengthen/shorten sim
-- load a new time
load_enable_n <= '0';
bcd_load_time <= x"1958";
WAIT FOR 5*PERIOD_C;
load_enable_n <= '1';
WAIT FOR 3 sec; -- adjust this time to lengthen/shorten sim
-- shutting down simulation
sim_done <= true;
WAIT FOR PERIOD_c*1;
-----------------------------------------------------------------------
-- This Last WAIT statement needs to be here to prevent the PROCESS
-- sequence from re starting.
-----------------------------------------------------------------------
WAIT;
END PROCESS stimulus;
END test;
...
seconds:PROCESS(reset_n,sec,clk,load_n)
BEGIN
if (reset_n = '1' OR sec > 59 OR load_n = '1') then
sec <= "0000000";
else
if(rising_edge(clk)) then
sec <= sec + 1;
...
if (reset_n = '1' OR sec > 59 OR load_n = '1') then