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Timer VHDL语言中的BCD定时器_Timer_Vhdl_Counter_Bcd - Fatal编程技术网

Timer VHDL语言中的BCD定时器

Timer VHDL语言中的BCD定时器,timer,vhdl,counter,bcd,Timer,Vhdl,Counter,Bcd,出于好奇,不久前刚开始使用VHDL 所以我试着在斯巴达3板上写BCD定时器 不知何故,我不明白为什么它总是显示“意外”错误 所以如果我想拥有如图片链接所示的功能, 如何修改代码?如有任何帮助,将不胜感激 可点击 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity w3 is Port ( clk : in STD_LOGIC; rst : in STD_LO

出于好奇,不久前刚开始使用VHDL

所以我试着在斯巴达3板上写BCD定时器

不知何故,我不明白为什么它总是显示“意外”错误

所以如果我想拥有如图片链接所示的功能, 如何修改代码?如有任何帮助,将不胜感激

可点击

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity w3 is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           stp : in  STD_LOGIC;
           an : out  STD_LOGIC_VECTOR (3 downto 0);
           c : out  STD_LOGIC_VECTOR (6 downto 0));
end w3;

architecture timer of w3 is
signal div1 : integer range 0 to 499999 :=0; -- 100Hz
signal ck100hz : std_logic; -- 100Hz output
signal div2 : integer range 0 to 249999 :=0; -- 200Hz
signal ck200hz : std_logic; -- 200Hz output
signal div3 : integer range 0 to 124999 :=0; -- 400Hz
signal ck400hz : std_logic; -- 400Hz output
signal index : integer range 0 to 9 :=0;
signal scan : std_logic_vector (3 downto 0);
signal S : std_logic;
signal disp : std_logic_vector (3 downto 0);

begin
process begin
wait until rising_edge(clk);
if div1 < 499999 then
    ck100hz <= '0';
    div1 <= div1+1;
else 
    ck100hz <= '1';
    div1 <= 0;
end if;
if div2 < 249999 then
    ck200hz <= '0';
    div2 <= div2+1;
else
    ck200hz <= '1';
    div2 <= 0;
end if;
if div3 < 124999 then
    ck400hz <= '0';
    div3 <= div3+1;
else
    ck400hz <= '1';
    div3 <= 0;
end if;
end process;

process begin
wait until rising_edge(clk);
if rst = '1' then 
    index <= 0; 
end if;
if stp = '1' then 
    index <= index; 
end if;

if ck100hz = '1' then
    if index < 3 then index <= index+1;
        else index <= 0;
        if index < 4 and index > 7 then index <= index+1;
            else index <= 0;
            if index < 8 and index > 11 then index <= index+1;
                else index <= 0;
                if index < 12 and index > 15 then index <= index+1;
                    else index <= 0;
   end if;
      end if;
          end if;
             end if;
end if;
end process;

process begin
wait until rising_edge(clk);
if ck400hz = '1' then
    With scan select -- error unexpected With
        an <= an(0) when "00",
              an(1) when "01",
              an(2) when "10",
              an(3) when others;
end if;
end process;

process begin
wait until rising_edge(clk);
if ck200hz = '1' then
    With S select   -- error unexpected With
    disp <= index integer range 0 to 3 when "00",
            index integer range 4 to 7 when "01",
            index integer range 8 to 11 when "10",
            index integer range 12 to 15 when others;
end if;
end process;




with index select
    C <= "1000000" when 0, 
          "1111001" when 1, 
          "0100100" when 2, 
          "0110000" when 3, 
          "0011001" when 4, 
          "0010010" when 5, 
          "0000010" when 6,
          "1111000" when 7,       
          "0000000" when 8,
          "0011000" when 9;

end timer;
对于低激活:
如果索引为0,则应将011111分配给C。您必须启用几乎所有的分段。现在,您的内部计算将处于高活动状态。由于PCB布局的原因,显示器本身的激活度较低,因此在将整个C向量分配给阴极端口之前,应将其反转:顺序代码(如进程)中不支持阴极。不需要这么多end if,使用elsif分支来最小化语句的深度。您不应该编写低活动代码。没有扫描ans S的驱动程序。@Paebells我以为这是一个高活动代码?你说没有扫描ans和S的驱动程序是什么意思?我不太熟悉elsif,所以我使用了很多end if。。。好的,如果在过程中不能使用with…select,那么我可以使用什么使函数工作?谢谢你的帮助。编辑:如果您不介意,请举例说明。ISE不支持-2008语法更改顺序选择的信号分配。ISE XST也不支持并发选择信号分配。顺序选择的信号分配具有等效的case语句。这不是一个代码编写服务,也许你会问一个特定的问题?a不正确,一次只能有一个元素为真,分配整个内容。未使用disp,您似乎没有BCD计数器,索引仅指定为0或其当前值。div1、div2和div3仅针对增量进行计算。@Paebles感谢您明确解释了elsif和rst、stp问题,我现在得到了这些部分。但我仍然不理解关于S和扫描没有驱动程序的部分,如果我想驱动这两个,我该怎么做?关于低活性部分,我做了一些扩展。@Paebles谢谢,我会继续尝试。你的解释让我有所收获,谢谢。
with index select
  C <= "1000000" when 0, 
       "1111001" when 1,
       -- ...
       "0011000" when 9;
with index select
  C <= "0111111" when 0, 
       "0000110" when 1,
       -- ...
       "1100111" when 9;

  Cathode_n <= not C;
if ck100hz = '1' then
  if index < 3 then
    index <= index+1;
  else
    index <= 0;
    if index < 4 and index > 7 then
      index <= index+1;
    else
      index <= 0;
      if index < 8 and index > 11 then
        index <= index+1;
      else
        index <= 0;
        if index < 12 and index > 15 then
          index <= index+1;
        else
          index <= 0;
        end if;
      end if;
    end if;
  end if;
end if;
if ck100hz = '1' then
  if index < 3 then
    index <= index+1;
  else
    if index < 4 and index > 7 then
      index <= index+1;
    else
      if index < 8 and index > 11 then
        index <= index+1;
      else
        if index < 12 and index > 15 then
          index <= index+1;
        else
          index <= 0;
        end if;
      end if;
    end if;
  end if;
end if;
if ck100hz = '1' then
  if index < 3 then
    index <= index + 1;
  elsif index < 4 and index > 7 then
    index <= index + 1;
  elsif index < 8 and index > 11 then
    index <= index + 1;
  elsif index < 12 and index > 15 then
    index <= index+1;
  else
    index <= 0;
  end if;
end if;
elsif index < 4 and index > 7 then
if ck100hz = '1' then
  if index < 3 then
    index <= index + 1;
  else
    index <= 0;
  end if;
end if;
if rst = '1' then 
  index <= 0; 
end if;
if stp = '1' then 
  index <= index; 
end if;

if ck100hz = '1' then
  -- ...
end if;
if rst = '1' then 
  index <= 0; 
elsif stp = '1' then 
  index <= index; 
elsif ck100hz = '1' then
  -- ...
end if;