Verilog 无法输入if-else语句

我写了这样的代码：

   if (a) begin
   //some coding
   end
   else begin
   stage = 0;
           if (b) begin
                  if (stage == 0) begin
                  stage = 1;
                  end
                  else if (stage == 1) begin
                  stage = 2;
                  end
                  else begin
                  stage = 0;
            end
            else
            // some coding
            end
    end

---

当stage为1时，stage==1中的代码无法执行。我的代码有什么问题吗？

这样说，它无法工作。 你必须把它放在一个过程中，即。always@something.

//adding a signal needed
reg[1:0] stage_next;     

always@(*)begin//Means that everytime an event occurs in one of the signals used in the following code,
               //the code contained in this process will be executed
    if (a) begin
   //some coding
    end
    else begin
    stage = 0;
            if (b) begin
                  if (stage == 0) begin
                  //stage = 1;//this assignement will produce a combinatorial loop
                            //when the value of 'stage' changes the process(always@(*))
                            //will be re-executed. You have to assign another signal(stage_next here)
                  stage_next = 1
                  end
                  else if (stage == 1) begin
                  //stage = 2;//Same here
                  stage_next = 2;
                  end
                  else begin
                  //stage = 0;//Same here
                  stage_next = 0;
            end
            else
            // some coding
            end
    end
end
//The other process where stage will take the value of stage_next should be synchronous
//It will break the combinatorial loop
always@(posedge clk)
  stage <= stage_next;

如果b在计算stage==1条件之前强制stage归零，则阻塞分配stage=0

---

使用非阻塞赋值我认为您的缩进是误导性的，请尝试：

   always @(*)
   if (a) begin
   //some coding
   end
   else begin
           stage = 1;
           if (b) begin
                  if (stage == 0) begin
                      stage = 1;
                  end
                  else if (stage == 1) begin
                      stage = 2;
                  end
                  else begin
                      stage = 0;
                  end
            end // Your code did not have this end
            else begin // This begin was also missing
            // some coding
            end
    end

所以我想你是说，如果你有那个代码，那么你看不到stage==2？？？

---

因为如果没有这些代码修改，您将使else绑定到一个意外的if

错误是什么？你能展示一些刺激吗？这是在一个总是@*或总是@posedge clk中吗？