使用verilog的4位乘法器，仅使用半加和全加器
我试图创建一个模拟4位乘法器而不使用乘法（*）的模块，只需要使用半加和全加，因此我成功地从某个实例编程解决方案，代码如下：使用verilog的4位乘法器，仅使用半加和全加器,verilog,Verilog,我试图创建一个模拟4位乘法器而不使用乘法（*）的模块，只需要使用半加和全加，因此我成功地从某个实例编程解决方案，代码如下： module HA(sout,cout,a,b); output sout,cout; input a,b; assign sout = a^b; assign cout = (a&b); endmodule module FA(sout,cout,a,b,cin); output sout,cout; input a,b,cin; assign sout =(a
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
module multiply4bits(product,inp1,inp2,clock,reset,load);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
input load;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
always @ (posedge clock )
begin
if(reset == 1)
begin
// something to reset
end
else if (load == 1)
begin
product[0] = (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
end
end
endmodule
Line 35: Instantiation is not allowed in sequential area except checker instantiation
Line 36: Instantiation is not allowed in sequential area except checker instantiation
Line 37: Instantiation is not allowed in sequential area except checker instantiation
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Line 46: Instantiation is not allowed in sequential area except checker instantiation
如果有人能帮助我，我将非常感激。你也可以这样做：
module mul4(ans,aa,bb,clk,load,);
input [3:0]aa,bb;
input load,clk;
output [7:0]ans;
reg rst;
always @(posedge clk)
begin
if(load)
rst=0;
else
rst=1;
end
multiply4bits mm(ans,aa,bb,cl,rst);
endmodule
module multiply4bits(product,inp1,inp2,clock,reset);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
assign product[0]= (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
希望能有所帮助。我不确定您现在想做什么，但您想这样做：（框中显示可控加法器，即，如果
m0bi