Verilog 使用模式开关的二进制到灰色代码和灰色到二进制

我用模式开关实现代码转换器，模式0表示二进制到灰色代码，模式1表示灰色到二进制转换。 我的设计和测试平台如下所示

设计

    module bin2gray(input [3:0] bin, output [3:0] G );
    
    assign G[3] = bin[3];
    assign G[2] = bin[3] ^ bin[2];
    assign G[1] = bin[2] ^ bin[1];
    assign G[0] = bin[1] ^ bin[0];
    
    endmodule
    
    module gray2bin (input [3:0] G, output [3:0] bin );
    
    assign bin[3] = G[3];
    assign bin[2] = G[3] ^ G[2];
    assign bin[1] = G[3] ^ G[2] ^ G[1];
    assign bin[0] = G[3] ^ G[2] ^ G[1] ^ G[0];
    
    endmodule
    
    module code_converter(in,mode_switch,out);
    input [3:0]in;
    input mode_switch;
    output [3:0] out;
    always @(in or mode_switch);
    if(mode_switch == 1'b1)
        gray2bin m2(in,out);
    else
        bin2gray m1(in,out);
    endmodule

试验台

    module tb();
    
        reg [3:0] in;
        reg mode_switch;
        wire [3:0] out;
     
    code_converter uut(.in(in),.mode_switch(mode_switch),.out(out));
        
       // stimulus
       initial  begin
    
        mode_switch <=0;       
            in <= 0; #10;
            in <= 1;   #10;
            in <= 2;   #10;
            in <= 3;   #10;
            in <= 4;   #10;
            in <= 5;   #10;
            in <= 6;   #10;
            in <= 7;   #10;
            in <= 8;   #10;
            in <= 9;   #10;
            in <= 10;  #10;
            in <= 11;  #10;
            in <= 12;  #10;
            in <= 13;  #10;
            in <= 14;  #10;
            in <= 15;  #10;
            #100;   
    
        mode_switch <=1;
            in <= 0; #10;
            in <= 1;   #10;
            in <= 2;   #10;
            in <= 3;   #10;
            in <= 4;   #10;
            in <= 5;   #10;
            in <= 6;   #10;
            in <= 7;   #10;
            in <= 8;   #10;
            in <= 9;   #10;
            in <= 10;  #10;
            in <= 11;  #10;
            in <= 12;  #10;
            in <= 13;  #10;
            in <= 14;  #10;
            in <= 15;  #10;
            #100;
          $stop;
       end
    initial begin
    $dumpvars;
    $dumpfile("sth.vcd");
    end
    endmodule

---

设计和语法有问题吗？

问题在于，您不能在运行时根据信号值有条件地实例化模块

可以添加两个实例，然后根据开关信号选择所需的实例输出

module code_converter(in,mode_switch,out);
    input [3:0]in;
    input mode_switch;
    output [3:0] out;
    wire [3:0] out_b2g;
    wire [3:0] out_g2b;

    assign out = (mode_switch) ? out_g2b : out_b2g;
    gray2bin m2 (in, out_g2b);
    bin2gray m1 (in, out_b2g);
endmodule

---

问题在于，您不能在运行时根据信号值有条件地实例化模块

可以添加两个实例，然后根据开关信号选择所需的实例输出

module code_converter(in,mode_switch,out);
    input [3:0]in;
    input mode_switch;
    output [3:0] out;
    wire [3:0] out_b2g;
    wire [3:0] out_g2b;

    assign out = (mode_switch) ? out_g2b : out_b2g;
    gray2bin m2 (in, out_g2b);
    bin2gray m1 (in, out_b2g);
endmodule