Verilog中输出和输出逻辑的区别是什么？

下面是示例1

   module my_fsm(clk, reset, X, Y, Z);
     input clk, reset, X;
     output Y, Z;
   endmodule 

下面是示例2

module my_fsm(clk, reset, X, Y, Z);
 input clk, reset, X;
 output logic Y, Z;
endmodule

---

如您所见，有输出Y，Z，还有输出逻辑Y，Z。Verilog中输出和输出逻辑的基本区别是什么？

logic关键字是在system Verilog中引入的。它避免了reg和导线之间的混淆

input a;
output reg x; //x is declared as a register
always@(posedge clk)
 x <= a;

另一种在方块上书写的方法

input a;
output logic x; //Here x is taken as a register since its used inside always block
always@(posedge clk)
x <= a;

input a;
output logic x;
assign x = a; //Here x is taken as a wire due to assign statement

---

根据IEEE 1800-2012中23.2.2.3确定端口类型、数据类型和方向的规则，两个示例是等效的。如果未指定端口类型，则假定为导线。所以，区别在于连线和逻辑。