Verilog 2个变量的3位浓缩

我正在努力理解这段Verilog代码

reg [2:0] SYNC;
always @(posedge clk) SYNC <= {SYNC[1:0], ASYNC};
wire SYNC_risingedge = (SYNC[2:1] == 2'b01);
wire SYNC_fallingedge = (SYNC[2:1] == 2'b10);
wire SYNC_on = ~SYNC[1];

reg[2:0]同步；
始终@（posedge clk）同步
问题1


问题2

二进制数01是否只放在第2位和第1位？如果是，它如何影响前一行

否，
==
是一项测试，而不是作业。如果这两个同步位匹配
2b'01
，则
SYNC\u risingedge
导线将为高电平。否则它会很低

注意：
SYNC\u risingedge
的“赋值”是异步的-它只是组合逻辑

问题3

与前一行相同的问题

同样的答案

问题4

[1]在~SYNC[1]中是什么意思

它只是指
SYNC
的第1位。当SYNC[1]处于低位时，SYNC_on处于高位，反之亦然

reg [2:0] SYNC;
always @(posedge clk) SYNC <= {SYNC[1:0], ASYNC}; *"does this mean that it concentrates         the state of ASYNC with only bits 1 and 0?"*
wire SYNC_risingedge = (SYNC[2:1] == 2'b01); *"is the binary number 01 placed only in  bits 2 and 1? if so, how does it affect the previous line?"*
wire SYNC_fallingedge = (SYNC[2:1] == 2'b10); *"same question as previous line"*
wire SYNC_on = ~SYNC[1]; *"What does the [1] mean in ~SYNC[1]?"*

always @(posedge clk) SYNC <= {SYNC[1:0], ASYNC};

   SYNC  |   ASYNC   |  New SYNC Setting
---------+-----------|--------------------
   000   |     0     |       000
   001   |     0     |       010
   010   |     0     |       100
   011   |     0     |       110
   100   |     0     |       000
   101   |     0     |       010
   110   |     0     |       100
   111   |     0     |       110
   000   |     1     |       001
   001   |     1     |       011
   010   |     1     |       101
   011   |     1     |       111
   100   |     1     |       001
   101   |     1     |       011
   110   |     1     |       101
   111   |     1     |       111

wire SYNC_risingedge = (SYNC[2:1] == 2'b01);

wire SYNC_fallingedge = (SYNC[2:1] == 2'b10);

wire SYNC_on = ~SYNC[1];