Vhdl 错误：Xst:827=无法合成信号计数，同步描述错误
我试图模拟电梯，结果得到了错误Vhdl 错误：Xst:827=无法合成信号计数，同步描述错误,vhdl,Vhdl,我试图模拟电梯，结果得到了错误 ERROR:Xst:827 = Signal count cannot be synthesized, bad synchronous description 我遵循这个来源的代码[因为我的非常相似，（我有7层楼和两个以上的电梯）。首先我使用视频中提到的代码，然后我将实现两个以上的电梯在这个模拟中一起工作 提前谢谢 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; u
ERROR:Xst:827 = Signal count cannot be synthesized, bad synchronous description
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity elevator is
port (clk: in std_logic;
sensors1: out std_logic:='0'; --sensors at each level for elevator 1
a1, a2, a3, a4, a5, a6, a7: out std_logic; -- for LED display at FPGA
insideopendoor, in1, in2, in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down: std_logic; -- input request for each floor
opendoor: out std_logic; -- from inside elevator
closedoor: out std_logic); -- from inside elevator
end elevator;
architecture sequence of elevator is
constant timedoorclose: integer := 3;
constant timedoorclosed: integer := 2;
constant time_nx_state: integer :=4;
signal demand: std_logic_vector(0 to 4) := "00000";
signal direction_of_elevator : integer range 0 to 2 := 0;
signal updownpassenger : std_logic := '0';
signal signalstatus: std_logic := '1';
type status is (L1, L2, L3, L4, L5);
signal pr_state, nx_state: status;
begin
main: process (clk, insideopendoor, in1, in2, in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down)
variable digit1 : std_logic_vector (6 downto 0);
variable count : integer range 0 to (time_nx_state + timedoorclose + timedoorclosed);
variable bufferopendoor : std_logic;
variable position : integer range 0 to 4;
variable tempup : integer range 1 to 2 := 1;
variable tempdown : integer range -4 to 4;
begin
if (clk'event and clk='1') then
demand(0) <= demand(0) or in1 or in1up or in1down;
demand(1) <= demand(1) or in2 or in2up or in2down;
demand(2) <= demand(2) or in3 or in3up or in3down;
demand(3) <= demand(3) or in4 or in4up or in4down;
demand(4) <= demand(4) or in5 or in5up or in5down;
case pr_state is
when L1 => position := 0;
when L2 => position := 1;
when L3 => position := 2;
when L4 => position := 3;
when L5 => position := 4;
end case;
for i in 1 to 4 loop
if demand(i) ='1' then
tempup := i - position;
else null;
end if;
end loop;
for i in 3 downto 0 loop
bufferopendoor := '1';
closedoor <= '0';
count := 0;
end loop; --
elsif (updownpassenger = '1') then
if (count < timedoorclose) then
opendoor <= '1';
bufferopendoor := '1';
elsif count < (timedoorclose + timedoorclosed) then
opendoor <= '0';
bufferopendoor := '0';
else
closedoor <= '0';
end if;
--else null; ------
--end if; ------
-----------part main-----------------
count := count +1;
if insideopendoor = '1' then
opendoor<='1';
bufferopendoor :='1';
closedoor <= '0';
count := 0;
elsif (updownpassenger ='1') then
if (count < timedoorclose) then
opendoor <= '1';
bufferopendoor := '1';
closedoor <= '0';
elsif (count < (timedoorclose + timedoorclosed)) then
opendoor <= '0';
bufferopendoor := '0';
closedoor <= '1';
else
closedoor <= '0';
pr_state <= nx_state;
if signalstatus = '1' then
signalstatus <= '0';
else
signalstatus <= '1';
end if;
count := 0;
end if;
else null; --
end if;--
case nx_state is
when L1 =>
digit1 := "1111001";
if demand(0) = '1' then
demand(0) <= '0';
else null;
end if;
when L2 =>
digit1 := "0100100";
if demand(1) = '1' then
demand(1) <= '0';
else null;
end if;
when L3 =>
digit1 := "0110000";
if demand(3) = '1' then
demand(3) <= '0';
else null;
end if;
when L4 =>
digit1 := "0011001";
if demand(3) = '1' then
demand(3) <= '0';
else null;
end if;
when L5 =>
digit1 := "0010010";
if demand(4) = '1' then
demand(4) <= '0';
else null;
end if;
when others => null;
end case;
a1 <= digit1(0);
a2 <= digit1(1);
a3 <= digit1(2);
a4 <= digit1(3);
a5 <= digit1(4);
a6 <= digit1(5);
a7 <= digit1(6);
end if;
end process main;
step: process (pr_state, signalstatus)
begin
case pr_state is
--end if;
when L1 =>
if (demand(0)='1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <=L2;
elsif direction_of_elevator = 2 then
nx_state <= pr_state;
else
nx_state <= pr_state;
end if;
end if;
when L2 =>
if (demand(1)= '1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L3;
elsif direction_of_elevator = 2 then
nx_state <= L1;
else
nx_state <= pr_state;
end if;
end if;
when L3 =>
if (demand(2)= '1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L4;
elsif direction_of_elevator = 2 then
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L5;
elsif direction_of_elevator = 2 then
end if;
end if;
end if;
when L5 =>
if (demand(4)='1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L4;
elsif direction_of_elevator = 2 then
nx_state <= L1;
else
nx_state <= pr_state;
end if;
end if;
when others => null;
end case;
end process step;
end sequence;
ieee库；
使用ieee.std_logic_1164.all；
使用ieee.std_logic_arith.all；
使用ieee.std_logic_unsigned.all；
实体电梯是
端口（时钟：在标准逻辑中；
传感器1:out std_逻辑：='0'；--电梯1各层的传感器
a1、a2、a3、a4、a5、a6、a7：输出标准逻辑——用于FPGA上的LED显示
INIDEOPENDOOR、in1、in2、in3、in4、in5、INUP、in2up、in3up、in4up、in5up、in5down、in4down、in3down、in2down、in1down：标准_逻辑；--每个楼层的输入请求
开门：外部标准逻辑；--从电梯内部
闭门：外部标准（U逻辑）；--从电梯内部
端部升降机；
电梯的结构顺序是
常数timedoorclose:整数：=3；
常数TimeDoor Closed:整数：=2；
恒定时间\u nx\u状态：整数=4；
信号需求：标准逻辑向量（0到4）：=“00000”；
_电梯信号方向_：整数范围0~2:=0；
信号上下乘客：标准_逻辑：='0'；
信号状态：标准逻辑：='1'；
类型状态为（L1、L2、L3、L4、L5）；
信号pr_状态，nx_状态：状态；
开始
主：进程（时钟、内部端点、in1、in2、in3、in4、in5、in1向上、in2向上、in3向上、in4向上、in5向上、in5向下、in4向下、in3向下、in2向下、in4向下）
变量digit1:std_逻辑_向量（6到0）；
变量计数：整数范围0到（时间nx状态+时间门关闭+时间门关闭）；
可变缓冲区打开门：标准_逻辑；
可变位置：0到4的整数范围；
变量tempup：整数范围1到2:=1；
变量tempdown：整数范围-4到4；
开始
如果（clk'事件和clk='1'），则
需求（0）位置：=4；
终例；
对于1到4循环中的i
如果需求（i）=‘1’，则
tempup:=i-位置；
否则无效；
如果结束；
端环；
对于3到0循环中的i
bufferopendoor:=“1”；
closedoor您的代码似乎非常混乱。它无法合成有一个特定的原因：当代码紧跟这一行时，请仔细思考
elsif (updownpassenger = '1') then
将被执行。它将在敏感度列表中任何输入的正边缘或负边缘后执行，除了clk
仅在负边缘后执行。您将如何设计具有这种行为的逻辑？嗯，您的合成器也不能这样做
基本上，你需要重构你的代码，你需要把它分成连续的和组合的过程。（组合逻辑是其输出仅取决于其输入的逻辑，因此是不包含锁存器或触发器的逻辑。顺序逻辑是包含锁存器或触发器的逻辑，但通常也包含一些门。不要使用锁存器-它们不是同步设计。）虽然有很多方法可以对这些过程进行编码，但明智的做法是坚持使用模板。以下是三个模板，如果遵循这些模板，将为您提供所需的一切，并使您的VHDL编码过程保持简单：
以下是异步复位顺序逻辑的模板，所有合成工具都应该了解：
process(clock, async_reset) -- nothing else should go in the sensitivity list
begin
-- never put anything here
if async_reset ='1' then -- or '0' for an active low reset
-- set/reset the flip-flops here
-- ie drive the signals to their initial values
elsif rising_edge(clock) then -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
-- put the synchronous stuff here
-- ie the stuff that happens on the rising or falling edge of the clock
end if;
-- never put anything here
end process;
以下是无异步重置的顺序逻辑的模板：
process(clock) -- nothing else should go in the sensitivity list
begin
-- never put anything here
if rising_edge(clock) then -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
-- put the synchronous stuff here
-- ie the stuff that happens on the rising or falling edge of the clock
end if;
-- never put anything here
end process;
下面是组合过程的相应模板：
process(all inputs in the sensitivity list) -- an 'input' is a signal either on the LHS of an assignment or a signal that is tested
begin
-- combinational logic (with complete assignment and no feedback)
end process;
如果你对这个答案投了反对票，你可能会说为什么，这样我才能改进它。