std_逻辑_向量的VHDL乘法

在模拟时，我得到了一个运行时错误，所以我尝试在Vivado中运行RTL分析，看看是否至少可以创建组件的原理图。我的代码如下：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity multiplicator_test is
    generic(
            WORD_SIZE: natural := 8;
            EXP_SIZE: natural := 3
        );
        port(
            input_1: in std_logic_vector(WORD_SIZE-1 downto 0);
            input_2: in std_logic_vector(WORD_SIZE-1 downto 0);
            result: out std_logic_vector(WORD_SIZE-1 downto 0)
        );
end entity multiplicator_test;

architecture multiplicator_test_arch of multiplicator_test is
    constant SIGNIFICAND_SIZE: natural := WORD_SIZE - EXP_SIZE - 1;

    signal significand: std_logic_vector(SIGNIFICAND_SIZE-1 downto 0) := (others => '0');
    signal exponent: std_logic_vector(EXP_SIZE-1 downto 0) := (others => '0');
    signal sign: std_logic := '0';
    signal aux: std_logic_vector((2*SIGNIFICAND_SIZE)-1 downto 0) := (others => '0');
begin
        aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
        significand <= aux(SIGNIFICAND_SIZE - 1 downto 0);
        exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));
        sign <= input_1(WORD_SIZE-1) or input_2(WORD_SIZE-1);
        result <= sign & exponent & significand;
end architecture multiplicator_test_arch;

exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));

运行分析时，我得到：

错误：[Synth 8-690]分配中的宽度不匹配；目标有3位，源有4位[…/multipador.vhd:27]

出现错误的行是27：

aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));

---

显然，目标aux是3位，但实际上应该是8位。

您发布的行不是第27行，第27行如下：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity multiplicator_test is
    generic(
            WORD_SIZE: natural := 8;
            EXP_SIZE: natural := 3
        );
        port(
            input_1: in std_logic_vector(WORD_SIZE-1 downto 0);
            input_2: in std_logic_vector(WORD_SIZE-1 downto 0);
            result: out std_logic_vector(WORD_SIZE-1 downto 0)
        );
end entity multiplicator_test;

architecture multiplicator_test_arch of multiplicator_test is
    constant SIGNIFICAND_SIZE: natural := WORD_SIZE - EXP_SIZE - 1;

    signal significand: std_logic_vector(SIGNIFICAND_SIZE-1 downto 0) := (others => '0');
    signal exponent: std_logic_vector(EXP_SIZE-1 downto 0) := (others => '0');
    signal sign: std_logic := '0';
    signal aux: std_logic_vector((2*SIGNIFICAND_SIZE)-1 downto 0) := (others => '0');
begin
        aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
        significand <= aux(SIGNIFICAND_SIZE - 1 downto 0);
        exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));
        sign <= input_1(WORD_SIZE-1) or input_2(WORD_SIZE-1);
        result <= sign & exponent & significand;
end architecture multiplicator_test_arch;

exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));

收益率：

---

您发布的行不是第27行，第27行是：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity multiplicator_test is
    generic(
            WORD_SIZE: natural := 8;
            EXP_SIZE: natural := 3
        );
        port(
            input_1: in std_logic_vector(WORD_SIZE-1 downto 0);
            input_2: in std_logic_vector(WORD_SIZE-1 downto 0);
            result: out std_logic_vector(WORD_SIZE-1 downto 0)
        );
end entity multiplicator_test;

architecture multiplicator_test_arch of multiplicator_test is
    constant SIGNIFICAND_SIZE: natural := WORD_SIZE - EXP_SIZE - 1;

    signal significand: std_logic_vector(SIGNIFICAND_SIZE-1 downto 0) := (others => '0');
    signal exponent: std_logic_vector(EXP_SIZE-1 downto 0) := (others => '0');
    signal sign: std_logic := '0';
    signal aux: std_logic_vector((2*SIGNIFICAND_SIZE)-1 downto 0) := (others => '0');
begin
        aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
        significand <= aux(SIGNIFICAND_SIZE - 1 downto 0);
        exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));
        sign <= input_1(WORD_SIZE-1) or input_2(WORD_SIZE-1);
        result <= sign & exponent & significand;
end architecture multiplicator_test_arch;

exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));

收益率：

---

我真不敢相信我犯了这么愚蠢的错误，非常感谢！我犯了很多愚蠢的错误：。很高兴我能帮忙。我真不敢相信我犯了这么愚蠢的错误，非常感谢！我犯了很多愚蠢的错误：。很高兴我能帮忙。