Vhdl 在Nexys2上运行FSM时遇到问题
我试图运行一个简单的FSM，其中LED被扫描。我通过将位向左移位应用了这个逻辑，使用了&运算符。它根本不移动，只有LSB发光，就是这样，我也用1.5Hz的时钟减慢了时钟。有人能告诉我这里出了什么问题吗Vhdl 在Nexys2上运行FSM时遇到问题,vhdl,fsm,Vhdl,Fsm,我试图运行一个简单的FSM，其中LED被扫描。我通过将位向左移位应用了这个逻辑，使用了&运算符。它根本不移动，只有LSB发光，就是这样，我也用1.5Hz的时钟减慢了时钟。有人能告诉我这里出了什么问题吗 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity scan is Port ( clk : in STD_LOGIC; le
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity scan is
Port (
clk : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0);
reset : in STD_LOGIC
);
end scan;
architecture Behavioral of scan is
Type state is
(
RESET_ST,
S1
);
signal n_state : state;
signal c_state : state;
signal input_temp :unsigned (7 downto 0):= "00000001";
begin
--------------------------------------------------------------------------
--------------------------CURRENT STATE ASSIGNMENT------------------------
--------------------------------------------------------------------------
STATE_ASSIGNMENT: process (clk, reset)
begin
if (reset = '1') then
c_state <= RESET_ST;
elsif (clk'event and clk = '1') then
c_state <= n_state;
end if;
end process STATE_ASSIGNMENT;
--------------------------------------------------------------------------
----------------------------- INTPUT BLOCK--------------------------------
--------------------------------------------------------------------------
INPUT_BLOCK : process (c_state)
begin
case (c_state) is
when RESET_ST =>
input_temp <= "00000001";
n_state <= S1;
when S1 =>
input_temp <= input_temp (6 downto 0) & '0';
n_state <= S1;
when others =>
n_state <= RESET_ST;
end case;
end process;
--------------------------------------------------------------------------
----------------------------- OUTPUT BLOCK--------------------------------
--------------------------------------------------------------------------
OUTPUT_BLOCK : process (c_state, input_temp)
begin
case (c_state) is
when RESET_ST =>
led <= std_logic_vector (input_temp);
when S1 =>
led <= std_logic_vector (input_temp);
when others =>
led <= (others => '1');
end case;
end process OUTPUT_BLOCK;
end Behavioral;
IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
使用IEEE.NUMERIC_STD.ALL；
实体扫描是
港口（
clk：标准逻辑中；
led：输出标准逻辑向量（7到0）；
复位：在标准逻辑中
);
结束扫描；
行为扫描的体系结构是
类型状态为
(
重置，
S1
);
信号n_状态：状态；
信号c_状态：状态；
信号输入温度：无符号（7到0）：=“00000001”；
开始
--------------------------------------------------------------------------
--------------------------当前状态分配------------------------
--------------------------------------------------------------------------
状态分配：进程（clk，重置）
开始
如果（重置='1'），则
c_state有两个显而易见的错误
第一个计数器没有声明（注释掉，很简单）
第二，有一次在S1 n_州，很抱歉，我忘了评论它，我没有使用任何。好的，如果我在灵敏度列表中添加下一个状态，即n_状态，它会工作吗？第二，是的，当它全部变成0时，我什么也看不到，但是换档部分呢？我明确定义了每个状态的输出，我应该在这里设置限制吗？a）不，灵敏度列表中的n_状态不会做任何事情b）将所有零移位仍然是所有零。你可以考虑每个LED被显示的状态，总共10个状态。如果州是一个热点，那么新的8个州可以分别驱动一个LED。这将定义一个约翰逊计数器。你能给我举个例子吗？这将有助于我更好地理解输入温度信号的调节方式。现在它处于一个组合过程中，输入温度不在灵敏度列表中。此外，在“其他”状态下未定义输入_temp，因此表示存在闩锁。您需要的是移位寄存器，顾名思义，输入_temp应在顺序（时钟）过程中进行调节。
architecture foo of scan is
type state is ( RESET_ST, S1 );
signal n_state: state;
signal c_state: state;
-- signal input_temp: unsigned (7 downto 0):= "00000001";
signal shft_reg: std_logic_vector (7 downto 1);
begin
state_assignment:
process (clk, reset)
begin
if reset = '1' then
c_state <= RESET_ST;
-- counter <= (others => '0');
shft_reg <= (others => '0');
elsif clk'event and clk = '1' then
c_state <= n_state;
if c_state = RESET_ST then
shft_reg <= shft_reg (6 downto 1) & '1';
elsif shft_reg /= "1000000" then
shft_reg <= shft_reg (6 downto 1) & '0';
end if;
end if;
end process;
--input_block :
NEXT_STATE:
process (c_state)
begin
case (c_state) is
when RESET_ST =>
-- input_temp <= "00000001";
n_state <= S1;
when S1 =>
-- input_temp <= input_temp (6 downto 0) & '0';
n_state <= S1;
when others =>
n_state <= RESET_ST;
end case;
end process;
-- output_block:
-- process (c_state, input_temp)
-- begin
-- case (c_state) is
-- when RESET_ST =>
-- led <= std_logic_vector (input_temp);
-- when S1 =>
-- led <= std_logic_vector (input_temp);
-- when others =>
-- led <= (others => '1');
-- end case;
-- end process;
-- LED0_OUT:
-- led(0) <= '1' when c_state = RESET_ST else '0';
LEDOUT:
process (c_state, shft_reg)
begin
if c_state = RESET_ST then
led(0) <= '1';
else
led(0) <= '0';
end if;
led (7 downto 1) <= shft_reg; -- shft_reg(7 downto 1)
end process;
end architecture foo;
library ieee;
use ieee.std_logic_1164.all;
entity scan_tb is
end entity;
architecture foo of scan_tb is
signal clk: std_logic := '0';
signal reset: std_logic := '1';
signal led: std_logic_vector ( 7 downto 0);
begin
DUT:
entity work.scan
port map (
clk => clk,
led => led,
reset => reset
);
CLOCK:
process
begin
wait for 0.33 sec; -- one half clock period, 1.5 Hz
clk <= not clk;
if Now > 20 sec then
wait;
end if;
end process;
STIMULUS:
process
begin
wait until rising_edge(clk);
wait for 0.33 sec;
wait until rising_edge(clk);
reset <= '0';
wait;
end process;
end architecture;
state_assignment:
process (clk, reset)
begin
if reset = '1' then
c_state <= RESET_ST;
-- counter <= (others => '0');
shft_reg <= (others => '0');
elsif clk'event and clk = '1' then
c_state <= n_state;
-- if c_state = RESET_ST then
if shft_reg = "0000000" then
shft_reg <= shft_reg (6 downto 1) & '1';
elsif shft_reg /= "1000000" then
shft_reg <= shft_reg (6 downto 1) & '0';
end if;
end if;
end process;
state_assignment:
process (clk, reset)
begin
if reset = '1' then
c_state <= RESET_ST;
-- counter <= (others => '0');
shft_reg <= (others => '0');
elsif clk'event and clk = '1' then
c_state <= n_state;
-- if c_state = RESET_ST then
if shft_reg = "0000000" then
shft_reg <= shft_reg (6 downto 1) & '1';
-- elsif shft_reg /= "1000000" then
else
shft_reg <= shft_reg (6 downto 1) & '0';
end if;
end if;
end process;
LEDOUT:
process (shft_reg)
begin
if shft_reg = "0000000" then
led(0) <= '1';
else
led(0) <= '0';
end if;
led (7 downto 1) <= shft_reg; -- shft_reg(7 downto 1)
end process;