VHDL中的Bundle语句
如何组合/捆绑语句以进一步使用和更好地处理?例如,像这样的一些赋值将在例程的未来调用中多次使用VHDL中的Bundle语句,vhdl,usability,Vhdl,Usability,如何组合/捆绑语句以进一步使用和更好地处理?例如,像这样的一些赋值将在例程的未来调用中多次使用 ADDR_PC <= "0000000000"; ADDR_OP_A <= "00000"; ADDR_OP_B <= "00000"; OP_CODE <= OP_NOP; OP_IMMED <= IMMED_NULL; WE_SREG <= "00000"; -- S V N C Z VHDL
ADDR_PC <= "0000000000";
ADDR_OP_A <= "00000";
ADDR_OP_B <= "00000";
OP_CODE <= OP_NOP;
OP_IMMED <= IMMED_NULL;
WE_SREG <= "00000"; -- S V N C Z
VHDL有记录(C称之为struct)
声明示例:
type T_MY_RECORD is record
Member1 : STD_LOGIC;
Member2 : STD_LOGIC_VECTOR(15 downto 0);
end record;
signal mySignal1 : T_MY_RECORD;
signal mySignal2 : T_MY_RECORD;
用法示例:
mySignal1 <= (
Member1 => '1',
Member2 => x"12FC"
);
mySignal2.Member1 <= '0';
mySignal1'1',
成员2=>x“12FC”
);
mySignal2.Member1记录和/或聚合:
library ieee;
use ieee.std_logic_1164.all;
entity op_decoded is
end entity;
architecture foo of op_decoded is
-- These declarations probably want to be in a package
constant IMMED_NULL: std_logic_vector (8 downto 0) := (others => '0');
constant OP_NOP: std_logic_vector (5 downto 0) := (others => '0');
type decode_op is
record
PC: std_logic_vector (7 downto 0);
OP_A: std_logic_vector (4 downto 0);
OP_B: std_logic_vector (4 downto 0);
OP_CODE: std_logic_vector (5 downto 0);
OP_IMMED: std_logic_vector (8 downto 0);
WE_SREG: std_logic_vector (4 downto 0); -- S V N C Z
end record;
constant NOP: decode_op := (
PC => "00000000",
OP_A => "00000",
OP_B => "00000",
OP_CODE => OP_NOP,
OP_IMMED => IMMED_NULL,
WE_SREG => "00000"
);
-- actual signals
signal ADDR_PC: std_logic_vector (7 downto 0);
signal ADDR_OP_A: std_logic_vector (4 downto 0);
signal ADDR_OP_B: std_logic_vector (4 downto 0);
signal OP_CODE: std_logic_vector (5 downto 0);
signal OP_IMMED: std_logic_vector (8 downto 0);
signal WE_SREG: std_logic_vector (4 downto 0);
signal pipe1: decode_op;
signal pipe_disc: decode_op;
begin
(ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <= NOP;
pipe1 <= NOP;
pipe_disc <= (pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE,
pipe1.OP_IMMED, pipe1.WE_SREG);
end architecture;
ieee库;
使用ieee.std_logic_1164.all;
实体op_已解码
终端实体;
op_的架构foo已解码
--这些声明可能需要放在一个包中
常数IMMED_NULL:std_逻辑_向量(8到0):=(其他=>'0');
常数OP_NOP:std_逻辑_向量(5到0):=(其他=>'0');
类型decode_op为
记录
PC:std_逻辑_向量(7到0);
OP_A:std_逻辑_向量(4到0);
OP_B:std_逻辑_向量(4到0);
操作码:标准逻辑向量(5到0);
OP_IMMED:std_逻辑_向量(8到0);
WE_SREG:std_logic_vector(4到0);--svncz
结束记录;
常数NOP:decode_op:=(
PC=>“00000000”,
OP_A=>“00000”,
OP_B=>“00000”,
OP_代码=>OP_NOP,
OP_IMMED=>IMMED_NULL,
WE_SREG=>“00000”
);
--实际信号
信号地址PC:标准逻辑向量(7到0);
信号ADDR_OP_A:std_逻辑_向量(4到0);
信号加法运算B:标准逻辑向量(4到0);
信号操作码:标准逻辑向量(5到0);
信号运算IMMED:标准逻辑向量(8到0);
信号WE_SREG:std_逻辑_向量(4到0);
信号管道1:解码操作;
信号管\盘:解码\操作;
开始
(ADDR_PC、ADDR_OP_A、ADDR_OP_B、OP_CODE、OP_IMMED、WE_SREG)记录和/或聚合是一种可能性,但另一种选择是在驱动信号的过程中声明一个过程,然后调用该过程,如:
process (clk_i) is
procedure NOP is
begin
ADDR_PC <= "0000000000";
ADDR_OP_A <= "00000";
ADDR_OP_B <= "00000";
OP_CODE <= OP_NOP;
OP_IMMED <= IMMED_NULL;
WE_SREG <= "00000"; -- S V N C Z
end procedure;
begin
if rising_edge(clk_i) then
...
NOP;
...
end if;
end process;
过程(clk_i)是
程序NOP是
开始
地址PC是常数还是信号?OP_代码是枚举吗?
(ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <=
decode_op'(pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE,
pipe1.OP_IMMED, pipe1.WE_SREG);
process (clk_i) is
procedure NOP is
begin
ADDR_PC <= "0000000000";
ADDR_OP_A <= "00000";
ADDR_OP_B <= "00000";
OP_CODE <= OP_NOP;
OP_IMMED <= IMMED_NULL;
WE_SREG <= "00000"; -- S V N C Z
end procedure;
begin
if rising_edge(clk_i) then
...
NOP;
...
end if;
end process;