Vhdl Xilinx EDK中的不透明platgen故障_Vhdl_Xilinx_Microblaze_Xilinx Edk_Virtex

Vhdl Xilinx EDK中的不透明platgen故障

vhdl

Vhdl Xilinx EDK中的不透明platgen故障,vhdl,xilinx,microblaze,xilinx-edk,virtex,Vhdl,Xilinx,Microblaze,Xilinx Edk,Virtex,这是运行在： Ubuntu 64 LTS Xilinx平台工作室14.7（lin64）我正在尝试运行随附的microblaze\u demo项目，但我遇到了一个非常无用的错误短错误日志不幸的是，据我所知，system\u microblaze\u 0\u wrapper_xst.srp从未创建过。由于大小原因，完整的比特流生成日志为我只是试着跟着——我以前从未用过微晶玻璃。我能做些什么来解决这个问题 system.mhs mpmc核心需要更新其版本，但以下代码与它们提供的代码完全相同

这是运行在：

Ubuntu 64 LTS
Xilinx平台工作室14.7（lin64）

我正在尝试运行随附的

microblaze\u demo

项目，但我遇到了一个非常无用的错误

短错误日志不幸的是，据我所知，

system\u microblaze\u 0\u wrapper_xst.srp

从未创建过。由于大小原因，完整的比特流生成日志为

我只是试着跟着——我以前从未用过微晶玻璃。我能做些什么来解决这个问题

system.mhs

mpmc

核心需要更新其版本，但以下代码与它们提供的代码完全相同：

 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX_pin, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX_pin, DIR = O
 PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT mpmc_0_SDRAM_Clk_pin = mpmc_0_SDRAM_Clk, DIR = O, SIGIS = CLK
 PORT mpmc_0_SDRAM_CE_pin = mpmc_0_SDRAM_CE, DIR = O
 PORT mpmc_0_SDRAM_CS_n_pin = mpmc_0_SDRAM_CS_n, DIR = O
 PORT mpmc_0_SDRAM_RAS_n_pin = mpmc_0_SDRAM_RAS_n, DIR = O
 PORT mpmc_0_SDRAM_CAS_n_pin = mpmc_0_SDRAM_CAS_n, DIR = O
 PORT mpmc_0_SDRAM_WE_n_pin = mpmc_0_SDRAM_WE_n, DIR = O
 PORT mpmc_0_SDRAM_BankAddr_pin = mpmc_0_SDRAM_BankAddr, DIR = O, VEC = [1:0]
 PORT mpmc_0_SDRAM_Addr_pin = mpmc_0_SDRAM_Addr, DIR = O, VEC = [11:0]
 PORT mpmc_0_SDRAM_DQ = mpmc_0_SDRAM_DQ, DIR = IO, VEC = [15:0]
 PORT mpmc_0_SDRAM_DM_pin = mpmc_0_SDRAM_DM, DIR = O, VEC = [1:0]
 PORT mpmc_0_MPMC_InitDone_pin = mpmc_0_MPMC_InitDone, DIR = O


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 8.30.a
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_125_0000MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_125_0000MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_125_0000MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_RX_pin
 PORT TX = fpga_0_RS232_TX_pin
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 4.03.a
 PORT CLKIN = CLK_S
 PORT CLKOUT0 = clk_125_0000MHz
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 3.00.a
 PORT Slowest_sync_clk = clk_125_0000MHz
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN mpmc
 PARAMETER INSTANCE = mpmc_0
 PARAMETER HW_VER = 6.06.a
 PARAMETER C_MEM_PARTNO = MT48LC8M16A2-75
 PARAMETER C_MEM_TYPE = SDRAM
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MPMC_BASEADDR = 0x85000000
 PARAMETER C_MPMC_HIGHADDR = 0x85ffffff
 PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000
 PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE MPMC_CTRL = mb_plb
 PORT MPMC_Clk0 = clk_125_0000MHz
 PORT MPMC_Rst = mb_reset
 PORT MPMC_Clk_Mem = clk_125_0000MHz
 PORT SDRAM_Clk = mpmc_0_SDRAM_Clk
 PORT SDRAM_CE = mpmc_0_SDRAM_CE
 PORT SDRAM_CS_n = mpmc_0_SDRAM_CS_n
 PORT SDRAM_RAS_n = mpmc_0_SDRAM_RAS_n
 PORT SDRAM_CAS_n = mpmc_0_SDRAM_CAS_n
 PORT SDRAM_WE_n = mpmc_0_SDRAM_WE_n
 PORT SDRAM_BankAddr = mpmc_0_SDRAM_BankAddr
 PORT SDRAM_Addr = mpmc_0_SDRAM_Addr
 PORT SDRAM_DQ = mpmc_0_SDRAM_DQ
 PORT SDRAM_DM = mpmc_0_SDRAM_DM
 PORT MPMC_InitDone = mpmc_0_MPMC_InitDone
END

这似乎是一个许可问题。哇，甚至是DRM的补丁？我试试看。@user1155120，很遗憾，它只适用于windows

 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX_pin, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX_pin, DIR = O
 PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT mpmc_0_SDRAM_Clk_pin = mpmc_0_SDRAM_Clk, DIR = O, SIGIS = CLK
 PORT mpmc_0_SDRAM_CE_pin = mpmc_0_SDRAM_CE, DIR = O
 PORT mpmc_0_SDRAM_CS_n_pin = mpmc_0_SDRAM_CS_n, DIR = O
 PORT mpmc_0_SDRAM_RAS_n_pin = mpmc_0_SDRAM_RAS_n, DIR = O
 PORT mpmc_0_SDRAM_CAS_n_pin = mpmc_0_SDRAM_CAS_n, DIR = O
 PORT mpmc_0_SDRAM_WE_n_pin = mpmc_0_SDRAM_WE_n, DIR = O
 PORT mpmc_0_SDRAM_BankAddr_pin = mpmc_0_SDRAM_BankAddr, DIR = O, VEC = [1:0]
 PORT mpmc_0_SDRAM_Addr_pin = mpmc_0_SDRAM_Addr, DIR = O, VEC = [11:0]
 PORT mpmc_0_SDRAM_DQ = mpmc_0_SDRAM_DQ, DIR = IO, VEC = [15:0]
 PORT mpmc_0_SDRAM_DM_pin = mpmc_0_SDRAM_DM, DIR = O, VEC = [1:0]
 PORT mpmc_0_MPMC_InitDone_pin = mpmc_0_MPMC_InitDone, DIR = O


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 8.30.a
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_125_0000MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_125_0000MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_125_0000MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_RX_pin
 PORT TX = fpga_0_RS232_TX_pin
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 4.03.a
 PORT CLKIN = CLK_S
 PORT CLKOUT0 = clk_125_0000MHz
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 3.00.a
 PORT Slowest_sync_clk = clk_125_0000MHz
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN mpmc
 PARAMETER INSTANCE = mpmc_0
 PARAMETER HW_VER = 6.06.a
 PARAMETER C_MEM_PARTNO = MT48LC8M16A2-75
 PARAMETER C_MEM_TYPE = SDRAM
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MPMC_BASEADDR = 0x85000000
 PARAMETER C_MPMC_HIGHADDR = 0x85ffffff
 PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000
 PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE MPMC_CTRL = mb_plb
 PORT MPMC_Clk0 = clk_125_0000MHz
 PORT MPMC_Rst = mb_reset
 PORT MPMC_Clk_Mem = clk_125_0000MHz
 PORT SDRAM_Clk = mpmc_0_SDRAM_Clk
 PORT SDRAM_CE = mpmc_0_SDRAM_CE
 PORT SDRAM_CS_n = mpmc_0_SDRAM_CS_n
 PORT SDRAM_RAS_n = mpmc_0_SDRAM_RAS_n
 PORT SDRAM_CAS_n = mpmc_0_SDRAM_CAS_n
 PORT SDRAM_WE_n = mpmc_0_SDRAM_WE_n
 PORT SDRAM_BankAddr = mpmc_0_SDRAM_BankAddr
 PORT SDRAM_Addr = mpmc_0_SDRAM_Addr
 PORT SDRAM_DQ = mpmc_0_SDRAM_DQ
 PORT SDRAM_DM = mpmc_0_SDRAM_DM
 PORT MPMC_InitDone = mpmc_0_MPMC_InitDone
END