VHDL加法器测试台
我是VHDL新手,我正在使用4个全加器制作一个4位加法器。我创建了一个测试台,以查看加法器是否工作,并在ans中获得UU值。从我读到的是,这个过程没有被执行。我不知道如何解决这个问题,任何帮助都将不胜感激 这是测试台VHDL加法器测试台,vhdl,Vhdl,我是VHDL新手,我正在使用4个全加器制作一个4位加法器。我创建了一个测试台,以查看加法器是否工作,并在ans中获得UU值。从我读到的是,这个过程没有被执行。我不知道如何解决这个问题,任何帮助都将不胜感激 这是测试台 ENTITY Adder4_Test IS END Adder4_Test; ARCHITECTURE behavior OF Adder4_Test IS -- Component Declaration for the Unit Under Test (UUT) COM
ENTITY Adder4_Test IS
END Adder4_Test;
ARCHITECTURE behavior OF Adder4_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Adder4
PORT(
X : IN STD_LOGIC_vector(3 downto 0);
Y : IN STD_LOGIC_vector(3 downto 0);
Ans : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC
);
END COMPONENT;
--Inputs
signal X : STD_LOGIC_vector(3 downto 0) := (others => '0');
signal Y : STD_LOGIC_vector(3 downto 0) := (others => '0');
--Outputs
signal Ans : STD_LOGIC_vector(3 downto 0);
signal Cout : STD_LOGIC;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Adder4 PORT MAP (
X,
Y,
Ans,
Cout
);
-- Clock process definitions
--<clock>_process :process
--begin
--<clock> <= '0';
--wait for <clock>_period/2;
--<clock> <= '1';
--wait for <clock>_period/2;
--end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--wait for 100 ns;
--wait for <clock>_period*10;
-- insert stimulus here
-- Case 1 that we are testing.
X <= "0000";
Y <= "0000";
wait for 10 ns;
assert ( Ans = "0000" )report "Failed Case 1 - Ans" severity error;
assert ( Cout = '0' ) report "Failed Case 1 - Cout" severity error;
wait for 40 ns;
-- Case 2 that we are testing.
X <= "1111";
Y <= "1111";
wait for 10 ns;
assert ( Ans = "1110" )report "Failed Case 2 - Ans" severity error;
assert ( Cout = '1' ) report "Failed Case 2 - Cout" severity error;
wait for 40 ns;
wait;
end process;
END;
实体加法器4_测试
末端加法器4_测试;
加法器4_测试的架构行为是
--被测单元(UUT)的组件声明
元件加法器4
港口(
X:标准逻辑向量(3到0);
Y:标准逻辑向量(3到0);
Ans:输出标准逻辑向量(3到0);
Cout:OUT标准逻辑
);
端部元件;
--投入
信号X:STD_逻辑_向量(3到0):=(其他=>'0');
信号Y:STD_逻辑_向量(3到0):=(其他=>'0');
--输出
信号Ans:标准逻辑向量(3到0);
信号输出:标准逻辑;
--端口列表中未检测到时钟。将下面替换为
--适当的端口名
--恒定周期:时间:=10纳秒;
开始
--实例化被测单元(UUT)
uut:Adder4端口映射(
X,,
Y
嗯,,
库特
);
--时钟进程定义
--_过程:过程
--开始
--在添加了您没有提供的上下文子句,将5N分为5N,并确保Addr4中所需的实体按正确的顺序进行了分析之后,我尝试使用ghdl运行模拟,在那里我立即得到了一条错误消息“
这是针对全加器的。看到它是一个3输入XOR,我添加了一个:
library ieee;
use ieee.std_logic_1164.all;
entity Xor_model is
Port (A: in std_logic;
B: in std_logic;
C: in std_logic;
Z: out std_logic
);
end entity;
architecture behavioral of Xor_model is
begin
Z <= A xor B xor C;
end behavioral;
在附录4中:
architecture Structure of Adder4 is
signal sum: std_logic_vector(3 downto 0);
b_adder0: FullAdder port map (X(0), Y(0), c0, sum(0), c1);
b_adder1: FullAdder port map (X(1), Y(1), c1, sum(1), c2);
b_adder2: FullAdder port map (X(2), Y(2), c2, sum(2), c3);
b_adder3: FullAdder port map (X(3), Y(3), c3, sum(3), Cout);
并向ans添加延迟分配和:
Ans'X')所有测试都不涉及测试台或组件声明如果答案不能解决您的实际问题,请澄清UU是否在以后实际更改为定义值。
Adder4.vhdl:28:1:warning: component instance "xorlabel" is not bound
Adder4.vhdl:12:15:warning: (in default configuration of fulladder(behavioral))
library ieee;
use ieee.std_logic_1164.all;
entity Xor_model is
Port (A: in std_logic;
B: in std_logic;
C: in std_logic;
Z: out std_logic
);
end entity;
architecture behavioral of Xor_model is
begin
Z <= A xor B xor C;
end behavioral;
((NOT X) AND (NOT Y) AND Cin) OR (X AND Y AND Cin) ; --after 5 ns;
architecture Structure of Adder4 is
signal sum: std_logic_vector(3 downto 0);
b_adder0: FullAdder port map (X(0), Y(0), c0, sum(0), c1);
b_adder1: FullAdder port map (X(1), Y(1), c1, sum(1), c2);
b_adder2: FullAdder port map (X(2), Y(2), c2, sum(2), c3);
b_adder3: FullAdder port map (X(3), Y(3), c3, sum(3), Cout);
Ans: out STD_LOGIC_vector (3 DOWNTO 0) := (others => '0');