Chisel 凿子/FIRRTL定义不同端口异常

我最近将我的一个大项目的凿子版本从3.1.1升级到3.4.0；但是，我得到了一堆

firrtl.passes.CheckHighFormLike$defNameDifferentitportsException

：

firrtl.passes.CheckHighFormLike$DefnameDifferentPortsException: : ports of extmodule XilinxSimpleDualPortNoChangeBRAM with defname XilinxSimpleDualPortNoChangeBRAM are different for an extmodule with the same defname
firrtl.passes.CheckHighFormLike$DefnameDifferentPortsException: : ports of extmodule XilinxSimpleDualPortNoChangeBRAM_1 with defname XilinxSimpleDualPortNoChangeBRAM are different for an extmodule with the same defname
// and so on 241 times

以下是XilinxSimpleDualPortNoChangeBRAM的定义及其依赖项：

class XilinxSimpleDualPortNoChangeBRAM(width: Int,
                                       depth: Int,
                                       performance: String="HIGH_PERFORMANCE",
                                       initFile: String="",
                                       ramStyle: String="block",
                                       val useReset: Boolean=false)
                                       extends BlackBox(Map("RAM_WIDTH" -> width,
                                                            "RAM_DEPTH" -> depth,
                                                            "RAM_PERFORMANCE" -> performance,
                                                            "INIT_FILE" -> initFile,
                                                            "RAM_STYLE" -> ramStyle))
                                       with HasBlackBoxResource with Memory {
    val io = IO(new XilinxSimpleDualPortBRAMBlackBoxIO(log2Ceil(depth), width))
    val acceptedRamStyles = Seq("block", "distributed", "registers", "ultra")
    require(acceptedRamStyles contains ramStyle)
    def write(wrAddr: UInt, wrData: UInt, wrEn: Bool): Unit = {
      io.wea := wrEn
      io.addra := wrAddr
      io.dina := wrData
    }

    def read(rdAddr: UInt, rdEn: Bool): UInt = {
      io.addrb := rdAddr
      io.regceb := rdEn
      io.enb := rdEn
      io.doutb
    }

    def defaultBindings(clock: Clock, reset: core.Reset): Unit = {
      io.clock := clock
      if(useReset)
        io.reset := reset
      else
        io.reset := false.B
    }
    setResource("/XilinxSimpleDualPortNoChangeBRAM.v")
}

trait Memory extends BaseModule {
  def read(rdAddr: UInt, rdEn: Bool): UInt
  def write(wrAddr: UInt, wrData: UInt, wrEn: Bool): Unit
  val latency: Int = 2
}

class XilinxSimpleDualPortBRAMIO(addrWidth: Int, dataWidth: Int) extends Bundle {
    val addra  = Input(UInt(addrWidth.W))
    val addrb  = Input(UInt(addrWidth.W))
    val dina   = Input(UInt(dataWidth.W))
    val wea    = Input(Bool())
    val enb    = Input(Bool())
    val regceb = Input(Bool())
    val doutb  = Output(UInt(dataWidth.W))

    override def cloneType = (new XilinxSimpleDualPortBRAMIO(addrWidth, dataWidth)).asInstanceOf[this.type]
}
class XilinxSimpleDualPortBRAMBlackBoxIO(addrWidth: Int, dataWidth: Int) extends XilinxSimpleDualPortBRAMIO(addrWidth, dataWidth) {
    val clock  = Input(Clock())
    val reset  = Input(Reset())

    override def cloneType = (new XilinxSimpleDualPortBRAMBlackBoxIO(addrWidth, dataWidth)).asInstanceOf[this.type]
}

Verilog资源XilinxSimpleDualPortNoChangeBRAM.v是Vivado中可用的BRAM实例化模板之一：

module XilinxSimpleDualPortNoChangeBRAM #(
  parameter RAM_WIDTH = 64,                       // Specify RAM data width
  parameter RAM_DEPTH = 512,                      // Specify RAM depth (number of entries)
  parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
  parameter INIT_FILE = "",                       // Specify name/location of RAM initialization file if using one (leave blank if not)
  parameter RAM_STYLE = "block"                   // Target memory type. Accepted values: block, distributed, registers, ultra (UltraScale+ only)
) (
  input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH
  input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH
  input [RAM_WIDTH-1:0] dina,          // RAM input data
  input wea,                           // Write enable
  input enb,                           // Read Enable, for additional power savings, disable when not in use
  input regceb,                        // Output register enable
  output [RAM_WIDTH-1:0] doutb,         // RAM output data
  input clock,                          // Clock
  input reset                          // Output reset (does not affect memory contents)
);

  (* ram_style = RAM_STYLE *) reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
  reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}};

  // The following code either initializes the memory values to a specified file or to all zeros to match hardware
  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
    end else begin: init_bram_to_zero
      integer ram_index;
      initial
        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
          BRAM[ram_index] = {RAM_WIDTH{1'b0}};
    end
  endgenerate

  always @(posedge clock) begin
    if (wea)
      BRAM[addra] <= dina;
    if (enb)
      ram_data <= BRAM[addrb];
  end

  //  The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register)
  generate
    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register

      // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
       assign doutb = ram_data;

    end else begin: output_register

      // The following is a 2 clock cycle read latency with improve clock-to-out timing

      reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}};

      always @(posedge clock)
        if (reset)
          doutb_reg <= {RAM_WIDTH{1'b0}};
        else if (regceb)
          doutb_reg <= ram_data;

      assign doutb = doutb_reg;

    end
  endgenerate

  //  The following function calculates the address width based on specified RAM depth
  function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule

---

更新2：显然，一些

XilinxSimpleDualPortNoChangeBRAM

正在使用较旧版本的

XilinxSimpleDualPortBRAMBlackBoxIO

，其中重置类型仍然是

Bool

，而不是

reset

。更改该选项解决了问题。

当引用特定黑盒时，此检查被认为不允许出现不可能的情况。也就是说，以下内容必须是正确的：

• 如果黑盒没有参数，则所有端口必须具有相同的名称、宽度和顺序
• 如果黑盒有参数，则所有端口必须具有相同的名称，且顺序相同（但可能具有不同的宽度）

这听起来像是您的示例正在生成违反后一个条件的黑盒（因为您的黑盒有参数），或者这暴露了FIRRTL编译器检查中的错误

实际的Verilog模块从未被检查过，不会在这里引起任何问题

您是否可以更新您的问题，以提供产生这些错误的FIRRTL IR？具体来说，

XilinxSimpleDualPortNoChangeBRAM

和

XilinxSimpleDualPortNoChangeBRAM\u 1

的第一个RRTL IR是什么样子的？这应该在类似“Foo.fir”的文件中。或者，您可以执行以下操作：

导入凿子3.stage.凿子阶段
/*注意：这是emitChirrtl（“chirrtl”），因为您希望从凿子发出FIRRTL*/
println（sivestage.emitChirrtl（新MyTopModule））

谢谢您的回答；我已经更新了我的问题。这两个看起来不错，我可以在本地编译。但是，您有241个该错误的实例，是吗？假设检查不坏，这表明具有该defname的某些extmodule具有不同的端口（重新排序/丢失/额外端口或不同类型）。虽然很痛苦，但您是否可以对此进行抽查以查找端口差异？对于不同的ExtModule，重置类型（异步重置与同步重置）的推断也可能有所不同，然后自定义转换将在稍后重新运行CheckHighForm。显然，一些

XilinxSimpleDualPortNoChangeBRAM

正在使用较旧版本的

XilinxSimpleDualPortBRAMBlackBoxIO

，其中重置类型仍然是

Bool

，而不是

reset

。改变现状解决了问题。再次感谢您澄清错误信息并为我指明正确的方向！

  extmodule XilinxSimpleDualPortNoChangeBRAM : 
    input addra : UInt<14>
    input addrb : UInt<14>
    input dina : UInt<1>
    input wea : UInt<1>
    input enb : UInt<1>
    input regceb : UInt<1>
    output doutb : UInt<1>
    input clock : Clock
    input reset : Reset
    
    defname = XilinxSimpleDualPortNoChangeBRAM
    parameter RAM_STYLE = "block"
    parameter RAM_WIDTH = 1
    parameter RAM_DEPTH = 16384
    parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE"
    parameter INIT_FILE = ""

  extmodule XilinxSimpleDualPortNoChangeBRAM_1 : 
    input addra : UInt<6>
    input addrb : UInt<6>
    input dina : UInt<518>
    input wea : UInt<1>
    input enb : UInt<1>
    input regceb : UInt<1>
    output doutb : UInt<518>
    input clock : Clock
    input reset : Reset
    
    defname = XilinxSimpleDualPortNoChangeBRAM
    parameter RAM_STYLE = "distributed"
    parameter RAM_WIDTH = 518
    parameter RAM_DEPTH = 64
    parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE"
    parameter INIT_FILE = ""