Enums 在传递带有向量的文件时,如何在测试台中使用enum?
基本上,我在一个包中声明了一个typedef枚举(在一个名为Definition.sv的文件中): 然后我编写了测试台:Enums 在传递带有向量的文件时,如何在测试台中使用enum?,enums,verilog,system-verilog,hdl,vivado,Enums,Verilog,System Verilog,Hdl,Vivado,基本上,我在一个包中声明了一个typedef枚举(在一个名为Definition.sv的文件中): 然后我编写了测试台: `timescale 1ns/1ps `include "Definition.sv" module ALU_TB (); /*Inputs*/ data_bus A, B; //data_bus is a typedef struct packed logic enA, enB; logi
`timescale 1ns/1ps
`include "Definition.sv"
module ALU_TB ();
/*Inputs*/
data_bus A, B; //data_bus is a typedef struct packed
logic enA, enB;
logic invA;
logic enC;
logic [4:0] amount;
shift_op sh_select;
alu_op alu_select;
/*Outputs*/
data_bus data_out, d_out_exp;
flags_t flags, flags_exp;
/*Testbench signals*/
logic clk;
int Vectors, Errors;
logic [110:0] VettoriTest[0:99];
ALU_TOP dut (A, B, enA, enB, invA, enC, amount,
sh_select, alu_select, data_out, flags);
always
begin
clk = 0; #5;
clk = 1; #5;
end
initial
begin
$readmemh("Vectors_ALU.txt", VettoriTest);
Vectors = 0;
Errors = 0;
end
always @(posedge clk)
begin
A = VettoriTest [Vectors][31:0] ;
B = VettoriTest [Vectors][63:32];
enA = VettoriTest [Vectors][64];
enB = VettoriTest [Vectors][65];
invA = VettoriTest [Vectors][66];
enC = VettoriTest [Vectors][67];
amount = VettoriTest [Vectors][72:68];
sh_select = VettoriTest [Vectors][74:73]; //Error
alu_select = VettoriTest [Vectors][78:75]; //Error
d_out_exp = VettoriTest [Vectors][110:79];
end
...
...
这是它的一部分,错误是:
枚举变量只能分配给同一个枚举类型的变量或其一个值
我使用的软件是Vivado。您必须转换数据类型。最简单的方法应该是:
sh_select=shift_op'(VettorTest[Vectors][74:73]);
alu_select=alu_op'(VettoriTest[Vectors][78:75]);
我不明白信息中有什么不清楚的地方?VettorTest是一系列逻辑向量,而sh_select是一个枚举。不应将非枚举分配给枚举。例如,您可以sh_select=LSR
,它应该是正确的。否则你需要施放。@Serge我如何施放向量?抱歉,我是sv新手。对于测试台,您可以使用动态$cast
操作符,它是不可合成的。对于rtl,应该使用case
或if
运算符创建转换函数。
`timescale 1ns/1ps
`include "Definition.sv"
module ALU_TB ();
/*Inputs*/
data_bus A, B; //data_bus is a typedef struct packed
logic enA, enB;
logic invA;
logic enC;
logic [4:0] amount;
shift_op sh_select;
alu_op alu_select;
/*Outputs*/
data_bus data_out, d_out_exp;
flags_t flags, flags_exp;
/*Testbench signals*/
logic clk;
int Vectors, Errors;
logic [110:0] VettoriTest[0:99];
ALU_TOP dut (A, B, enA, enB, invA, enC, amount,
sh_select, alu_select, data_out, flags);
always
begin
clk = 0; #5;
clk = 1; #5;
end
initial
begin
$readmemh("Vectors_ALU.txt", VettoriTest);
Vectors = 0;
Errors = 0;
end
always @(posedge clk)
begin
A = VettoriTest [Vectors][31:0] ;
B = VettoriTest [Vectors][63:32];
enA = VettoriTest [Vectors][64];
enB = VettoriTest [Vectors][65];
invA = VettoriTest [Vectors][66];
enC = VettoriTest [Vectors][67];
amount = VettoriTest [Vectors][72:68];
sh_select = VettoriTest [Vectors][74:73]; //Error
alu_select = VettoriTest [Vectors][78:75]; //Error
d_out_exp = VettoriTest [Vectors][110:79];
end
...
...