Operating system Gem5缓存转储

如何将不同级别缓存中的所有数据转储到gem5中的一个文件中？ 或者我们可以通过它来分析缓存中的数据，就像我们可以借助计算机来分析管道一样

    util/O3-pipeview.py m5out/pipeview.txt --color -w150
    less -r o3-pipeview.out

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可以使用gem5中的调试标志“缓存””来理解icache和dcache输出。 我尝试了以下步骤：

连接到gem5基本目录

在终端上键入以下命令-

输出文件cache_pipe在m5out文件夹中生成。
看起来像-

2000: system.cpu.icache: sendMSHRQueuePacket: MSHR ReadReq [44c:44f] IF                              
2000: system.cpu.icache: createMissPacket: created ReadCleanReq [440:47f] IF from ReadReq [44c:44f] IF
2000: system.mem_ctrls.dram: Timing access to addr 1088, rank/bank/row 0 0 0                   
2000: system.mem_ctrls.dram: Activate at tick 2000                                        
2000: system.mem_ctrls.dram: Activate bank 0, rank 0 at tick 2000, now got 1 active          
2000: system.mem_ctrls.dram: Schedule RD/WR burst at tick 27500                             
46250: system.mem_ctrls.dram: number of read entries for rank 0 is 0                         
77000: system.cpu.icache: recvTimingResp: Handling response ReadResp [440:47f] IF
77000: system.cpu.icache: Block for addr 0x440 being updated in Cache                          
77000: system.cpu.icache: Block addr 0x440 (ns) moving from  to state: 6 (E) writable: 1 readable: 1 dirty: 0 | tag: 0 secure: 0 valid: 1 | set: 0x11 way: 0                                 
79000: system.cpu: T0 : 0x1044c @_start    :   mov   fp, #0             : IntAlu :  D=0x0000000000000000                                                                        
79000: system.cpu.icache: access for ReadReq [450:453] IF hit state: 6 (E) writable: 1 readable: 1 dirty: 0 | tag: 0 secure: 0 valid: 1 | set: 0x11 way: 0                                    
85000: system.cpu: T0 : 0x10450 @_start+4    :   mov   lr, #0             : IntAlu :  D=0x0000000000000000                                                                         
85000: system.cpu.icache: access for ReadReq [454:457] IF hit state: 6 (E) writable: 1 readable: 1 dirty: 0 | tag: 0 secure: 0 valid: 1 | set: 0x11 way: 0                                  
87000: system.cpu.dcache: access for ReadReq [8de50:8de53] miss                               
89000: system.cpu.dcache: sendMSHRQueuePacket: MSHR ReadReq [8de50:8de53]
89000: system.cpu.dcache: createMissPacket: created ReadSharedReq [8de40:8de7f] from ReadReq [8de50:8de53]

这里我使用DRAM、Exec和Cache标志，可以使用just Cache来获取有关icache和dcache的信息。 我使用了预编译的hello可执行文件，您可以使用自己的可执行文件集

2000: system.cpu.icache: sendMSHRQueuePacket: MSHR ReadReq [44c:44f] IF                              
2000: system.cpu.icache: createMissPacket: created ReadCleanReq [440:47f] IF from ReadReq [44c:44f] IF
2000: system.mem_ctrls.dram: Timing access to addr 1088, rank/bank/row 0 0 0                   
2000: system.mem_ctrls.dram: Activate at tick 2000                                        
2000: system.mem_ctrls.dram: Activate bank 0, rank 0 at tick 2000, now got 1 active          
2000: system.mem_ctrls.dram: Schedule RD/WR burst at tick 27500                             
46250: system.mem_ctrls.dram: number of read entries for rank 0 is 0                         
77000: system.cpu.icache: recvTimingResp: Handling response ReadResp [440:47f] IF
77000: system.cpu.icache: Block for addr 0x440 being updated in Cache                          
77000: system.cpu.icache: Block addr 0x440 (ns) moving from  to state: 6 (E) writable: 1 readable: 1 dirty: 0 | tag: 0 secure: 0 valid: 1 | set: 0x11 way: 0                                 
79000: system.cpu: T0 : 0x1044c @_start    :   mov   fp, #0             : IntAlu :  D=0x0000000000000000                                                                        
79000: system.cpu.icache: access for ReadReq [450:453] IF hit state: 6 (E) writable: 1 readable: 1 dirty: 0 | tag: 0 secure: 0 valid: 1 | set: 0x11 way: 0                                    
85000: system.cpu: T0 : 0x10450 @_start+4    :   mov   lr, #0             : IntAlu :  D=0x0000000000000000                                                                         
85000: system.cpu.icache: access for ReadReq [454:457] IF hit state: 6 (E) writable: 1 readable: 1 dirty: 0 | tag: 0 secure: 0 valid: 1 | set: 0x11 way: 0                                  
87000: system.cpu.dcache: access for ReadReq [8de50:8de53] miss                               
89000: system.cpu.dcache: sendMSHRQueuePacket: MSHR ReadReq [8de50:8de53]
89000: system.cpu.dcache: createMissPacket: created ReadSharedReq [8de40:8de7f] from ReadReq [8de50:8de53]