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hdl verilog编译器错误

verilog

hdl verilog编译器错误,verilog,Verilog,当我第一次尝试编译代码时，我只有语法错误，并且能够修复它们。现在我有一些我根本无法理解的错误。我不知道怎么修理 这是我目前的代码： module p_5 (output y_out, input x_in, clk, reset_b); parameter s_a = 2'd0; parameter s_b = 2'd1; parameter s_c = 2'd2; reg Set_flag; reg Clr_flag; reg [1:0] st

当我第一次尝试编译代码时，我只有语法错误，并且能够修复它们。现在我有一些我根本无法理解的错误。我不知道怎么修理

这是我目前的代码：

module p_5 (output y_out, input x_in, clk, reset_b);
    parameter s_a = 2'd0;
    parameter s_b = 2'd1;
    parameter s_c = 2'd2;

    reg Set_flag;
    reg Clr_flag;
    reg [1:0] state, next_state;
    assign y_out = (state == s_b) || (state == s_c) ;
    always @ (posedge clk)
     if (reset_b == 1'b0) state <= s_a;
     else state <= next_state;

    always @ (state, x_in, flag) begin
     next_state = s_a;
     Set_flag = 0;
     Clr_flag = 0;
     case (state)
         s_a: if ((x_in == 1'b1) && (flag == 1'b0))
            begin next_state = s_a; Set_flag = 1; end
            else if ((x_in == 1'b1) && (flag == 1'b1))
            begin next_state = s_b; Set_flag = 0; end 
            else if (x_in == 1'b0) next_state = s_a;
         s_b: if (x_in == 1'b0) next_state = s_b;
            else begin next_state = s_c; Clr_flag = 1; end
         s_c: if (x_in == 1'b0) next_state = s_c;
            else next_state = s_a;
         default: begin next_state = s_a; Clr_flag = 1'b0; Set_flag = 1'b0; end
      endcase
end

always @ (posedge clk)
    if (reset_b == 1'b0) flag <= 0;
    else if (Set_flag) flag <= 1'b1;
    else if (Clr_flag) flag <= 1'b0;
endmodule
错误：

p5.v:22: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0'
p5.v:22: error: Unable to elaborate condition expression.
p5.v:17: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0'
flag
p5.v:36: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
p5.v:37: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
p5.v:38: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
7 error(s) during elaboration.
您在p5.v中反复引用值
标志
，但它没有在任何地方声明为输入、注册或连接

添加适当的声明，应该解决该问题

p5.v:22: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0'
p5.v:22: error: Unable to elaborate condition expression.
p5.v:17: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0'
flag
p5.v:36: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
p5.v:37: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
p5.v:38: error: Could not find variable ``flag'' in ``t_ques_5_50.M0''
7 error(s) during elaboration.