阻塞和非阻塞分配Verilog
我有以下代码,在always block中有阻塞(代码1)和非阻塞(代码2)赋值 但在这两种情况下,产出是不同的。为什么? 我知道事件队列,但可能无法理解“always@(clk)”语句将被放置在事件队列中的什么位置阻塞和非阻塞分配Verilog,verilog,Verilog,我有以下代码,在always block中有阻塞(代码1)和非阻塞(代码2)赋值 但在这两种情况下,产出是不同的。为什么? 我知道事件队列,但可能无法理解“always@(clk)”语句将被放置在事件队列中的什么位置 // Code 1 module osc2 (clk, d); output clk; reg clk; input d; initial begin #10 clk = 0; $mo
// Code 1
module osc2 (clk, d);
output clk;
reg clk;
input d;
initial
begin
#10 clk = 0;
$monitor ("%d %b", $time, clk);
end
initial #100 $finish;
always @ (clk) #10 clk = ~clk;
endmodule
// Output of Code 1
10 0
20 1
// Code 2
module osc2 (clk, d);
output clk;
reg clk;
input d;
initial
begin
#10 clk = 0;
$monitor ("%d %b", $time, clk);
end
initial #100 $finish;
always @ (clk) #10 clk <= ~clk;
endmodule
// Output of Code 2
10 0
20 1
30 0 (goes on upto 90)
90 0
//代码1
模块osc2(时钟,d);
输出时钟;
注册时钟;
输入d;
首字母
开始
#10时钟=0;
$monitor(“%d%b”,$time,clk);
结束
初始#100美元完成;
始终@(clk)#10 clk=~clk;
端模
//代码1的输出
10 0
20 1
//代码2
模块osc2(时钟,d);
输出时钟;
注册时钟;
输入d;
首字母
开始
#10时钟=0;
$monitor(“%d%b”,$time,clk);
结束
初始#100美元完成;
always@(clk)#10 clk为了便于解释,我解开了前两个循环的内容,并展开了分解组件。下面的代码将进行模拟
始终@(clk)#10 clk=~clk代码>
initial while (1) // to see the loop, functionally equivalent to 'always'
begin // procedural block
begin : loop0_unraveled
@(clk); // suspend continuation of loop until change in clk
#10; // suspend continuation of loop 10 time units
clk = ~clk; /* eval '~clk' now
* update clk now
*/
end
begin : loop1_unraveled
begin // this block is functionally equivalent to '@(clk)'
reg smpl_clk; // local variable
smpl_clk = clk; // sample
$display("%t::Pre-Suspend : smpl_clk=%b clk=%b", $time, smpl_clk, clk);
wait(clk != smpl_clk); // suspend continuation of loop until
/* 1. no other blocking statements can execute, go to next region
* 2. All other regions are empty
* 3. Remaining events are block
* 4. Nothing left to do, exit simulation
*/
$display("%t::Post-Suspend : smpl_clk=%b clk=%b", $time, smpl_clk, clk);
end
#10; // unreachable
clk = ~clk;
end
end
initial while (1) // to see the loop, functionally equivalent to 'always'
begin // procedural block
begin : loop0_unraveled
@(clk); // suspend continuation of loop until change in clk
#10; // suspend continuation of loop 10 time units
clk <= ~clk; /* eval '~clk' now,
* update clk after all blocking statements are suspended
*/
end
begin : loop1_unraveled
begin // this block is functionally equivalent to '@(clk)'
reg smpl_clk; // local variable
smpl_clk = clk; // sample
$display("%t::Pre-Suspend : smpl_clk=%b clk=%b",$time, smpl_clk, clk);
wait(clk != smpl_clk); // suspend continuation of loop until true
/* 1. no other blocking statements can execute, go to next region
* 2. In NBA region update clk
* 3. Go back to active region
* 4. Eval true, continue
*/
$display("%t::Post-Suspend : smpl_clk=%b clk=%b", $time, smpl_clk, clk);
end
#10; // reached
clk <= ~clk;
end
end // Go to top of the loop
始终(clk)#10 clk这是几天前提出的同一个问题。格雷格回答得很好。谢谢russell,我读过了,但还是有些困惑。将在~clk或执行clk=时准确安排事件的时间,然后???&总是将@event放在哪个事件队列中???@KaranShah,除了clk@Greg之外的所有内容,非常感谢您提供这两个线程。它增强了我对事件队列和调度的概念,但我请求您,如果您能给我代码1的while循环迭代(事件队列语句),那么它将有助于我完全理解。
initial begin
#10 clk = 0;
forever #10 clk = ~clk;
end
always #10 clk = (clk===1'b0);