Verilog 如何将代码简化为一个模块？

我不知道如何简化这段代码，使其只实例化seg7一次。我是verilog新手，所以我没有任何线索。目前的代码运行良好，我只需要知道如何简化它。如果你们都能看一下代码，告诉我我需要做什么，我将非常感激

module Design (SW, HEX0,HEX1,HEX2,HEX3);
    input [3:0]SW;
    output [0:6]HEX0;
    output [0:6]HEX1;
    output [0:6]HEX2;
    output [0:6]HEX3;

    seg7hex3 disp1(SW[3:0],HEX3);
    seg7hex2 disp2(SW[3:0],HEX2);
    seg7hex1 disp3(SW[3:0],HEX1);
    seg7hex0 disp4(SW[3:0],HEX0);
endmodule

module seg7hex3(bcd,leds);
    input [3:0] bcd;
    output reg[1:7] leds;

    always @(bcd)
        case(bcd) //abcdefg
            0: leds = 7'b0000000; // b1111111 for active high (B)
            1: leds = 7'b0110001; // b1001110 (C)
            3: leds = 7'b0000000; // b1111111 (B)
            4: leds = 7'b0100100; // b1011011 (S)
            5: leds = 7'b0001111; // b1110000 (-)
            6: leds = 7'b0100100; // b1011011 (S)
            default: leds =7'bx;
    endcase

endmodule

module seg7hex2(bcd,leds);
    input [3:0] bcd;
    output reg[1:7] leds;

    always @(bcd)
        case(bcd) //abcdefg
            0: leds = 7'b0001000; // b1110111 for active high (A)
            1: leds = 7'b1001000; // b0110111 (H)
            3: leds = 7'b0110000; // b1001111 (E)
            4: leds = 7'b0000001; // b1111110 (O)
            5: leds = 7'b0111001; // b1000110 (|)
            6: leds = 7'b0000001; // b1111110 (O)
            default: leds =7'bx;
    endcase

endmodule

module seg7hex1(bcd,leds);
    input [3:0] bcd;
    output reg[1:7] leds;

    always @(bcd)
        case(bcd) //abcdefg
            0: leds = 7'b1110001; // b0001110 for active high (L)
            1: leds = 7'b1111001; // b0000110 (I)
            3: leds = 7'b0110000; // b1001111 (E)
            4: leds = 7'b0111000; // b1000111 (F)
            5: leds = 7'b1110001; // b0001110 ( first edge half V)
            6: leds = 7'b1000010; // b0111101 (d)
            default: leds =7'bx;
    endcase

endmodule

module seg7hex0(bcd,leds);
    input [3:0] bcd;
    output reg[1:7] leds;

    always @(bcd)
        case(bcd) //abcdefg
            0: leds = 7'b1110001; // b0001110 for active high (L)
            1: leds = 7'b0011000; // b1100111 (P)
            3: leds = 7'b0001000; // b1110111 (R)
            4: leds = 7'b0001000; // b1110111(A)
            5: leds = 7'b1000111; // b0111000 (back edge half V)
            6: leds = 7'b0001000; // b1110111 (A)
            default: leds =7'bx;
    endcase

endmodule

---

将所有always块放在一个模块中如何（见下文）？这里是链接。看起来您正在将相同的bcd值传递给所有se7hex模块，因此，您可以通过仅使用一个bcd输入并将所有always块更改为always@（bcd），而不是四个bcd输入来简化我的代码

如果只有一个bcd输入，还可以将所有情况合并到一个始终块中：

always @(bcd)
    case(bcd) //abcdefg
            0: begin
                leds1 = 7'b0000000; // b1111111 for active high (B)
                leds2 = 7'b0001000; // b1110111 for active high (A)
                leds3 = 7'b1110001; // b0001110 for active high (L)
                leds4 = 7'b1110001; // b0001110 for active high (L)\
            end
            1: begin
                ...
            end
            ...
    endcase

---

我还建议将硬编码输出更改为参数，以便将来更易于阅读和更改。例如

参数B=7'b000000
参数C=7'b10011100:leds1=B
1:leds1=C。将来，如果您的显示更改，您可以在一个位置更改参数。
always @(bcd)
    case(bcd) //abcdefg
            0: begin
                leds1 = 7'b0000000; // b1111111 for active high (B)
                leds2 = 7'b0001000; // b1110111 for active high (A)
                leds3 = 7'b1110001; // b0001110 for active high (L)
                leds4 = 7'b1110001; // b0001110 for active high (L)\
            end
            1: begin
                ...
            end
            ...
    endcase