SystemVerilog近；"完:synt错误，意外结束_Verilog_System Verilog

SystemVerilog近；"完:synt错误，意外结束

verilog system-verilog

SystemVerilog近；"完:synt错误，意外结束,verilog,system-verilog,Verilog,System Verilog,其他问题似乎缺少分号，不知道我可能在哪里？否则，会是什么 //fa module module full_adder( input logic sum, cout, output logic x, y, cin);//interface logic //internal signals logic c1, c2, s1; //circuit always_comb begin s1 = x^y; c1 = x&y; sum = s1^cin; c2 = s

其他问题似乎缺少分号，不知道我可能在哪里？否则，会是什么

 //fa module

module full_adder(
    input logic sum, cout,
    output logic    x, y, cin);//interface logic

//internal signals
logic c1, c2, s1;

//circuit
always_comb
begin
s1 = x^y;
c1 = x&y;
sum = s1^cin;
c2 = s1&cin;
cout = c1|c2;
end

end module

您是指

endmodule

而不是

endmodule