SystemVerilog$fdisplay韩元'；t打印看起来像格式说明符的字符串

我维护一个SystemVerilog库，在使用这段代码的3年中从未出现过这个问题。 我只能假设用户正在编译/运行某些特殊版本的VCS

Compiler version L-2016.06-SP2-7_Full64; Runtime version L-2016.06-SP2-7_Full64
----------------------------------------------------------------
OVM-2.1.2

确切的错误是：

Error-[STASKE_NEAFFS] Insufficient number of arguments
my_model/my_source_file.sv, 659
  Number of arguments (2) passed to substitute format specifiers in the string
  are less than the number of format specifiers.
  Please check the call stack shown above and pass number of arguments equal 
  to number of format specifiers.

即使某些格式说明符未“填写”，是否有办法强制打印

$fdisplay

？ 还是告诉风投们忽略这些问题

目前我唯一的调试方法是尝试添加一个相同字符串的

$display

，看看我是否注意到了什么

这里有一段非常类似的代码，是为UVM编写的。。。发生错误的实际代码对内部开发的OVM RAL层执行相同的操作。对靠近最末端的

$fdisplay

的调用是发生错误的等效行：

task save_uvm_accesses();
    uvm_reg_block model_reg_blocks[$];
    uvm_reg regs_of_block[$];
    uvm_reg_field fields_of_reg[$];
    uvm_reg sub_block;
    uvm_reg_file uvm_file;
    uvm_reg_backdoor backdoor_access;
    uvm_reg_frontdoor front_access;

    int fd;
    string output_file_name = "UVM_info.csv";
    string current_line="";
    string frontdoors = "";
    string fieldnames = "";

    reg_model.get_blocks(model_reg_blocks);
    fd = $fopen({output_file_name}, "w");
    $fdisplay(fd,"reg_name,reg_full_name,unique_file_name,reg_file,backdoor_access,front_access,access methods,fieldnames");
    $display("**************** UVM dump regs *******************");

    // go through each sub-block
    foreach (model_reg_blocks[sub_block]) begin
        // go through each reg in sub-block
        regs_of_block = {};
        model_reg_blocks[sub_block].get_registers(regs_of_block);
        foreach (regs_of_block[rreg]) begin
            uvm_reg_map reg_map[$];
            frontdoors = "\"";
            fieldnames = "\"";
            fields_of_reg = {};
            current_line ="";
            uvm_file = regs_of_block[rreg].get_regfile();
            regs_of_block[rreg].get_maps(reg_map);
            //backdoor_access = regs_of_block[rreg].get_backdoor(1);
            backdoor_access = model_reg_blocks[sub_block].get_backdoor(1);

            // enumerate any available frontdoor accesses
            foreach (reg_map[map]) begin
                front_access = regs_of_block[rreg].get_frontdoor(reg_map[map]);
                if(front_access != null)
                    frontdoors = {frontdoors, $sformatf("%s,", front_access.get_name())};
            end
            frontdoors = {frontdoors, "\""};

            regs_of_block[rreg].get_fields(fields_of_reg);
            foreach (fields_of_reg[current_fieldname]) begin
                fieldnames = {fieldnames, $sformatf("%s, ", fields_of_reg[current_fieldname].get_name())};
            end
            fieldnames = {fieldnames, "\""};
  
            //  current_line = {current_line, $sformatf("%s,", rreg}; r
            current_line = {current_line, $sformatf("%s,", regs_of_block[rreg].get_name())};
            current_line = {current_line, $sformatf("%s,", regs_of_block[rreg].get_full_name())};
            current_line = {current_line, $sformatf("%s,", model_reg_blocks[sub_block].get_name())};
            if(uvm_file == null)
                current_line = {current_line, "null,"};
            else
                current_line = {current_line, $sformatf("%s,", uvm_file.get_name())};
            if(backdoor_access == null)
                current_line = {current_line, "null,"};
            else
                current_line = {current_line, $sformatf("%s,", backdoor_access.get_name())};
            current_line = {current_line, $sformatf("%s,", frontdoors)};
            current_line = {current_line,"backdoor,"};
            current_line = {current_line, fieldnames};
            $fdisplay(fd, current_line);
        end
    end
    $fclose(fd);
endtask: save_uvm_accesses

---

最后，我将最后一行fdisplay更改为：

$fdisplay（fd，当前行）

到

$fdisplay（fd，“%s”，当前行）
显示我的一个信号路径在RAL返回的字符串中有
%A
。。。这可能会让人困惑
$fdisplay
。如何“强制”
$fdisplay
只打印我提供的内容？