Verilog I'；我有一个不可避免的Quartus语法错误

以下是我编写的代码：

reg number;
always @(posedge clk)
begin
case(SW[3:1])
        000: number = 32h'A65D;
        001: number = 32h'BAB9;
        010: number = 32h'9430;
        011: number = 32h'8BEB;
        100: number = 32h'7CB8;
        101: number = 32h'62F1;
        110: number = 32h'6EF9;
        111: number = 32h'5D5C;
        default: number = 32h'0000;
endcase
end

我在quartus中不断发现一个错误，每行都会说：

错误（10170）：文本“h”附近的test.v（181）处出现Verilog HDL语法错误； 期待”；“”

---

如何解决此错误？

您需要为<代码>编号指定位宽度；它当前为1位宽，您可能需要32位。您需要为每个案例项目添加大小和基数（

3'b

）：

reg [31:0] number;
always @(posedge clk)
begin
case(SW[3:1])
        3'b000: number <= 32'hA65D;
        3'b001: number <= 32'hBAB9;
        3'b010: number <= 32'h9430;
        3'b011: number <= 32'h8BEB;
        3'b100: number <= 32'h7CB8;
        3'b101: number <= 32'h62F1;
        3'b110: number <= 32'h6EF9;
        3'b111: number <= 32'h5D5C;
        default: number <= 32'h0000;
endcase
end

reg[31:0]编号；
始终@（posedge clk）
开始
案例（SW[3:1]）
3'b000:number您需要为
32'hA65D
更改
32h'A65D
。这将解决您的错误

reg [31:0]number
always @(posedge clk)
begin
case(SW[3:1])
3'b000: number <= 32'hA65D;
3'b001: number <= 32'hBAB9;
    3'b010: number <= 32'h9430;
    3'b011: number <= 32'h8BEB;
    3'b100: number <= 32'h7CB8;
    3'b101: number <= 32'h62F1;
    3'b110: number <= 32'h6EF9;
    3'b111: number <= 32'h5D5C;
endcase

reg[31:0]编号
始终@（posedge clk）
开始
案例（SW[3:1]）
3'b000:编号