Vhdl 在7段上运行十进制数时出现问题
我是初学者,请原谅我的代码逻辑。我试图通过计数器在7段上显示20个值。当该值大于9时,将选择第二段。当我运行这段代码时,我的第一个片段闪烁得非常快,第二个片段熄灭。我知道我在为段赋值的情况下犯了一些错误。我错过了什么?我的预设值是48Hz。有什么想法吗Vhdl 在7段上运行十进制数时出现问题,vhdl,Vhdl,我是初学者,请原谅我的代码逻辑。我试图通过计数器在7段上显示20个值。当该值大于9时,将选择第二段。当我运行这段代码时,我的第一个片段闪烁得非常快,第二个片段熄灭。我知道我在为段赋值的情况下犯了一些错误。我错过了什么?我的预设值是48Hz。有什么想法吗 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity counter is Port ( clk : in STD_LOGIC;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
segment : out STD_LOGIC_VECTOR (6 downto 0);
anode: out std_logic_vector (3 downto 0) );
end counter;
architecture Behavioral of counter is
constant prescaler: STD_LOGIC_VECTOR(16 downto 0) := "00000000000110000";
signal prescaler_counter: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
signal counter: std_logic_vector (19 downto 0):= (others => '0');
signal r_anode: std_logic_vector (3 downto 0):= (others => '0');
begin
process (clk) begin
if (clk'event and clk = '1') then
prescaler_counter <= std_logic_vector (unsigned(prescaler_counter) + 1);
if(prescaler_counter = prescaler) then
counter <= std_logic_vector (unsigned(counter)+1);
end if;
end if;
end process;
anode <= r_anode;
process (counter) begin
if (counter > "00000000000000001001") then
r_anode <= "1110";
else
r_anode <= "1101";
end if;
case counter is
when "00000000000000000000" => segment <= "0000001"; --0
when "00000000000000000001" => segment <= "1001111"; --1
when "00000000000000000010" => segment <= "0010010"; --2
when "00000000000000000011" => segment <= "0000110"; --3
when "00000000000000000100" => segment <= "1001100"; --4
when "00000000000000000101" => segment <= "0100100"; --5
when "00000000000000000110" => segment <= "0100000"; --6
when "00000000000000000111" => segment <= "0001111"; --7
when "00000000000000001000" => segment <= "0000000"; --8
when "00000000000000001001" => segment <= "0000100"; --9
when others => segment <= "1111111";
end case;
end process;
end Behavioral;
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.NUMERIC_STD.ALL;
实体计数器为
端口(时钟:在标准逻辑中;
段:输出标准逻辑向量(6到0);
阳极:输出标准逻辑向量(3到0);
末端计数器;
计数器的结构是
常数预分频器:标准逻辑向量(16到0):=“00000000000110000”;
信号预分频器\计数器:标准\逻辑\向量(16向下至0):=(其他=>'0');
信号计数器:标准逻辑向量(19到0):=(其他=>“0”);
信号r_阳极:标准逻辑向量(3到0):=(其他=>'0');
开始
进程(clk)开始
如果(clk'事件和clk='1'),则
预分频器计数器48Hz对于一个数字的10个值循环似乎仍然非常快,但如果这是您想要的。。。(顺便说一句,如果你放慢速度,问题可能会变得更加明显)
问题在于您的计数过程、您如何设置r\u阳极
,以及您的案例陈述,以确定段
的值,可能还有其他因素
你的计数过程从1到,嗯,很多,你只想到20,据我所知。您可能需要考虑添加一个环绕条件。不过,这取决于您如何执行以下操作
r\u阳极
在10个时钟周期内为“1110”
,然后在剩余的2^20个周期内为“1101”
。我认为这不是你想要的。顺便说一句,使用numeric\u std
,您可以只写unsigned(counter)>9
——我不确定您写的东西是否应该编译(我想您以前使用的是std\u logic\u unsigned
)
这是主要问题。您似乎希望两个数字的值都依赖于这一个计数器,但您正在比较整个20位计数器值,因此段仅在2^20中的10个时钟中处于活动状态,并且仅在第一个数字中处于打开状态,因为您只显式检查值0到9。您需要的是某种模数运算(或每个数字的单独计数器,或其他)
你可能还需要考虑如何驱动这两个显示器,但是这取决于你如何解决其他问题。
< P>我是在准备好显示的时候。它可以提供照明:
注:为了方便起见,我使用了10纳秒的时钟
第一个数字经过它的计数(在段上看到),然后切换到另一个数字,谁的段显示其他选择):
进程(计数器)
开始
如果(计数器>“0000000000000000 1001”),则
我发布了这段代码,多亏了@fru1bat和@David,我才发现了我的错误。是的,我用的是一个20位的计数器,我真的很笨,所以我用了一个5位的计数器,用这个延迟代码来减慢我的时钟
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity delay is
Port ( clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (31 downto 0);
flag : out STD_LOGIC);
end delay;
architecture Behavioral of delay is
signal count :integer:=0;
begin
process(clk) begin
if(clk'event and clk='1') then
count <= count +1; --increment counter.
end if;
--see whether counter value is reached,if yes set the flag.
if(count = to_integer (unsigned(a))) then
count <= 0;
flag <='1';
else
flag <='0';
end if;
end process;
end Behavioral
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.NUMERIC_STD.ALL;
实体延迟是
端口(时钟:在标准逻辑中;
a:标准逻辑向量(31到0);
标志:输出标准(U逻辑);
结束延迟;
行为延迟的体系结构是
信号计数:整数:=0;
开始
进程(clk)开始
如果(clk'事件和clk='1'),则
数一数你的柜台为什么这么大?在我看来,你的计数器在很短的时间内只会小于“1001”,然后在很长一段时间内它会大于这个数字,所以你的r_阳极信号几乎从未设置为“1101”。这是你的第二部分吗?哪个是哪个?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity delay is
Port ( clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (31 downto 0);
flag : out STD_LOGIC);
end delay;
architecture Behavioral of delay is
signal count :integer:=0;
begin
process(clk) begin
if(clk'event and clk='1') then
count <= count +1; --increment counter.
end if;
--see whether counter value is reached,if yes set the flag.
if(count = to_integer (unsigned(a))) then
count <= 0;
flag <='1';
else
flag <='0';
end if;
end process;
end Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
segment : out STD_LOGIC_VECTOR (6 downto 0);
anode: out std_logic_vector (3 downto 0) );
end counter;
architecture Behavioral of counter is
component delay
Port ( clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (31 downto 0);
flag : out STD_LOGIC);
end component;
signal flag : std_logic :='0';
signal delay_needed : std_logic_vector(31 downto 0);
constant countvalue: STD_LOGIC_VECTOR (4 downto 0) := "01001";
signal counter: std_logic_vector (4 downto 0):= (others => '0');
signal r_anode: std_logic_vector (3 downto 0):= (others => '0');
begin
delay_needed <= "00000001011111010111100001000000"; --25000000 in binary
inst_delay : delay port map(clk,delay_needed,flag);
process (flag) begin
if (flag'event and flag = '1') then
counter <= std_logic_vector (unsigned(counter)+1);
if (counter = countvalue) then
counter <= (others => '0');
end if;
end if;
end process;
anode <= r_anode;
r_anode <= "1110";
process (counter, r_anode) begin
case r_anode is
when "1110" => case counter is
when "00000" => segment <= "0000001"; --0
when "00001" => segment <= "1001111"; --1
when "00010" => segment <= "0010010"; --2
when "00011" => segment <= "0000110"; --3
when "00100" => segment <= "1001100"; --4
when "00101" => segment <= "0100100"; --5
when "00110" => segment <= "0100000"; --6
when "00111" => segment <= "0001111"; --7
when "01000" => segment <= "0000000"; --8
when "01001" => segment <= "0000100"; --9
when others => segment <= "1111111";
end case;
when others => segment <= "1111111";
end case;
end process;
end Behavioral;