Vhdl 子程序中的信号参数不受支持错误
我的代码是关于一个使用VHDL和maxplus2的乒乓球游戏。我不能让它被遵守Vhdl 子程序中的信号参数不受支持错误,vhdl,Vhdl,我的代码是关于一个使用VHDL和maxplus2的乒乓球游戏。我不能让它被遵守 library ieee; use ieee.std_logic_1164.all; -- use ieee.std_logic_unsigned.all; -- use ieee.std_logic_arith.all; entity center is port ( clk: in std_logic; ca: in std_logic;
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_arith.all;
entity center is
port (
clk: in std_logic;
ca: in std_logic;
cb: in std_logic;
enable: in std_logic;
a: in std_logic;
b: in std_logic;
ball: out std_logic_vector(16 downto 0);
sa: out std_ulogic;
sb: out std_ulogic;
over: inout std_ulogic
);
end center;
architecture behavior of center is
signal direction : integer range 0 to 2;
signal num : integer range -1 to 17;
begin
process (enable,ca,cb,a,b,clk)
begin
if enable = '0' then
over <= '0';
sa <= '0';
sb <= '0';
elsif enable = '1' and rising_edge(clk) then
if direction = 2 then
if ca = '1' then
direction <= 0;
num <= 1;
elsif cb = '1' then
direction <= 1;
num <= 16;
else
direction <= 2;
num <= 8;
end if;
elsif direction = 0 and num > 0 then
if b = '1' then
if num < 2 then
num <= num - 1;
direction <= 1;
else
direction <= 2;
sa <= '1' after 10 ns;
sb <= '0' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif direction = 1 and num <= 16 then
if a = '1' then
if num >= 14 then
num <= num + 1;
direction <= 2;
else
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif direction = 0 and num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
elsif direction = 0 and num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
end process;
end architecture behavior;
ieee库；
使用ieee.std_logic_1164.all；
--使用ieee.std_logic_unsigned.all；
--使用ieee.std_logic_arith.all；
实体中心是
港口（
clk：标准逻辑中；
ca：标准逻辑中；
cb：标准逻辑中；
启用：在std_逻辑中；
答：标准逻辑；
b：标准逻辑；
ball:out标准逻辑向量（16到0）；
sa:out std_ulogic；
sb:out std_ulogic；
结束：inout std_ulogic
);
端部中心；
中心的建筑行为是
信号方向：0到2的整数范围；
信号数：整数范围-1到17；
开始
进程（启用、ca、cb、a、b、clk）
开始
如果enable='0'，则
我想正如David所说的，你需要提供更多的信息。
在我看来，您正在编写一个测试台，上面的代码无法正确合成。ISE将告诉您语法正常，但延迟被忽略，即after
关键字。仅用于模拟
也就是说我会清理代码，因为有很多冗余。FX
最后两个elsif
语句。只需要一个。以及敏感度列表。只有clk
和enable
应该在那里
我已尝试清理您的代码：
process (enable,clk)
begin
if enable = '0' then
over <= '0';
sa <= '0';
sb <= '0';
elsif rising_edge(clk) then
case( direction ) is
when 0 =>
if num > 0 then
if b = '1' then
if num < 2 then
num <= num - 1;
direction <= 1;
else
direction <= 2;
sa <= '1' after 10 ns;
sb <= '0' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
when 1 =>
if num <= 16 then
if a = '1' then
if num >= 14 then
num <= num + 1;
direction <= 2;
else
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
end if;
when 2 =>
if ca = '1' then
direction <= 0;
num <= 1;
elsif cb = '1' then
direction <= 1;
num <= 16;
else
direction <= 2;
num <= 8;
end if;
when others => NULL;
end case ;
end if;
end process;
进程（启用，时钟）
开始
如果enable='0'，则
通过此代码分析。除应模拟的多余灵敏度列表项外，注意信号分配中的延迟机制（
之后的延迟机制）通常被忽略，不会导致合成后的延迟。此代码中没有用户编写的子程序。你的问题似乎在别处。这段代码中没有子程序。您确定发送了正确的代码段吗？你在哪一行得到错误？