VHDL:只能是';0';或';1';,而不是'';X'';L'';H';,或';U';用于case语句?

VHDL:只能是';0';或';1';,而不是'';X'';L'';H';,或';U';用于case语句?,vhdl,Vhdl,VHDL中是否有一种数据类型是类似于“std_逻辑_向量”的数组,而不是全部具有9种可能的状态: 'U': uninitialized. This signal hasn't been set yet. 'X': unknown. Impossible to determine this value/result. '0': logic 0 '1': logic 1 'Z': High Impedance 'W': Weak signal, can't tell if it shoul

VHDL中是否有一种数据类型是类似于“std_逻辑_向量”的数组,而不是全部具有9种可能的状态:

'U': uninitialized. This signal hasn't been set yet. 
'X': unknown. Impossible to determine this value/result. 
'0': logic 0 
'1': logic 1 
'Z': High Impedance 
'W': Weak signal, can't tell if it should be 0 or 1. 
'L': Weak signal that should probably go to 0 
'H': Weak signal that should probably go to 1 
'-': Don't care. 
'0': logic 0 
'1': logic 1 
只有两种可能的状态:

'U': uninitialized. This signal hasn't been set yet. 
'X': unknown. Impossible to determine this value/result. 
'0': logic 0 
'1': logic 1 
'Z': High Impedance 
'W': Weak signal, can't tell if it should be 0 or 1. 
'L': Weak signal that should probably go to 0 
'H': Weak signal that should probably go to 1 
'-': Don't care. 
'0': logic 0 
'1': logic 1 
我之所以问这个问题,是因为我在寻找verilog case语句的VHDL等价物。Verilog示例:

module m1(input a, input b, output reg[7:0] q);
wire [1:0] sel = {a, b};
always @* begin
    case(sel)
    2'b00: q = 8'd1;
    2'b01: q = 8'd2;
    2'b10: q = 8'd3;
    2'b11: q = 8'd4;
    endcase
end 
endmodule
在VHDL中,我可以毫无问题地执行此操作:

entity m1 is
    port(
        a :in std_logic;
        b :in std_logic;
        q :out std_logic_vector(7 downto 0)
    );
end entity;
m1的架构rtl是 信号选择:标准逻辑向量(1到0); 开始
sel q尝试使用软件包标准中的VHDL预定义类型:

type bit is ('0', '1');
type bit_vector is array (natural range <>) of bit;

funciton to_stdlogicvector (b :bit_vector)  return std_logic_vector;
function to_bitvector      (s :std_ulogic_vector) return bit_vector;
类型位为('0','1');
类型bit_向量是位的数组(自然范围);
函数返回标准逻辑向量(b:位向量);
函数返回位向量(s:std_ulogic_vector);
m1的架构rtl是 信号选择:标准逻辑向量(1到0); 信号bv:位_向量(1到0); 开始
sel你应该坚持使用
std_logic
std_logic_vector
,另一篇文章介绍了它们的区别:

我认为你的问题也来自这样一个事实:你把一个
整数
放入
标准逻辑向量
。应使用以下转换函数:

  • to_unsigned(arg:natural,size:natural)返回unsigned
  • std\u logic\u vector(arg:有符号或无符号)返回std\u logic\u vector
这让你想到:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all; --DO NOT FORGET THIS LIBRARY TO USE THE CONVERSION FUNCTION

entity m1 is
    port(
        a :in std_logic;
        b :in std_logic;
        q :out std_logic_vector(7 downto 0)
    );
end entity;

architecture rtl of m1 is
    signal sel :std_logic_vector(1 downto 0);
begin
    sel <= a & b;

    process(sel)
    begin
        case sel is
        when "00" => q <= std_logic_vector(to_unsigned(1,q'length));
        when "01" => q <= std_logic_vector(to_unsigned(2,q'length));
        when "10" => q <= std_logic_vector(to_unsigned(3,q'length));
        when "11" => q <= std_logic_vector(to_unsigned(4,q'length));
        when others => q <= std_logic_vector(to_unsigned(1,q'length));
        end case;
   end process;

end architecture;
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.numeric_std.all--不要忘记使用此库的转换功能
实体m1是
港口(
答:标准逻辑;
b:标准逻辑;
q:输出标准逻辑向量(7到0)
);
终端实体;
m1的体系结构rtl是
信号选择:标准逻辑向量(1到0);
开始

sel q另一种情况在模拟中很有用如果你有一些奇怪的信号进来,你将把XXs放在q上-这在波形上很有用。当“11”
时,很多人通常会忽略
,而当其他人
时,只将最后一个案例放在
中,但这也涵盖了错误状态-可能会掩盖错误。如果将slv转换为位向量,情况也是如此。评估
sel
的case语句没有其他选项,该问题会提示OP的问题。IEEE Std 1076-2008 10.8案例说明要求(在本标准的所有修订版中)表达式
sel
的每个值都包含在选项集中,并且“其他选项仅允许作为最后一个选项,并且作为其唯一选项;它代表先前选项中未给出的所有值(可能无)。”,我纠正了那个错误,改进了我的答案。ThanksIt无法将抽象文字的类型指定为数组类型(
q
)。这就是air78的答案来自使用从自然类型的抽象文字(数字)到std_逻辑_向量的转换。