Vhdl 中缀运算符没有可行的条目“=&引用；[硬件描述语言]

我一直在为交通灯控制器编写状态机

-- Ampelsteuerung mit Zähler und FSM Componente

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity AMPLSTRG is 
    port (  CLK, B1, RES : in bit;
            MAINRE, MAINYE, MAINGR : out bit;
            FARMRE, FARMYE, FARMGR : out bit);
end AMPLSTRG;

architecture FUNKTION of AMPLSTRG is
type AMP_STATE is (S0, S1, S2, S3, S4, S5, S6, S7, S8); -- Typendefinition
signal SCLR : bit;
signal CYCLES : unsigned (4 downto 0);
signal STATE, NEXT_STATE : AMP_STATE;                   -- STATE = aktueller Status, NEXT_STATE nächster Status (Typenzuweisung)
begin
-- COUNTER Prozess
CO: process (CLK)
begin
    if CLK = '1' and CLK'event then
        if SCLR = '1' then
            CYCLES <= (others => '0');                  -- 'others' = gesamten Vektor auf '0' setzten
        else
            CYCLES <= CYCLES + 1;
        end if;
    end if;
end process CO;

AMP_SYNC: process (CLK, RES)
begin
    if RES = '1' then
        STATE <= S0 after 5 ns;
        SCLR <= '1' after 5 ns;
    elsif CLK = '1' and CLK'event then
        STATE <= NEXT_STATE after 5 ns;                 -- Zustandszuweisung
    end if;
end process AMP_SYNC;

AMP_KOMB: process (STATE, B1, CYCLES)
begin
    -- default Werte Setzen
    MAINRE <= '0' after 5 ns; 
    MAINYE <= '0' after 5 ns;
    MAINGR <= '0' after 5 ns;

    FARMRE <= '0' after 5 ns; 
    FARMYE <= '0' after 5 ns; 
    FARMGR <= '0' after 5 ns;

    NEXT_STATE <= STATE; 
    SCLR <= '0';

    case STATE is
        when S0 => if B1 = '1' then 
                        MAINGR <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;
                        NEXT_STATE <= S1 after 5 ns;
                        SCLR <= '1' after 5 ns;
                    else                                -- MAINGR | FARMRE until B1 pressed
                        MAINGR <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;
                        SCLR <= '1' after 5 ns;
                   end if;

        when S1 => if CYCLES = '5' then 
                        MAINGR <= '0' after 5 ns;
                        MAINYE <= '1' after 5 ns;               
                        NEXT_STATE <= S2 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINGR | FARMRE for 5 sec
                        MAINGR <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;
                    end if;

        when S2 => if CYCLES = '5' then                         MAINRE <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;               
                        NEXT_STATE <= S3 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINYE | FARMRE for 5 sec
                        MAINYE <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;
                    end if;

        when S3 => if CYCLES = '2' then 
                        MAINRE <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;
                        FARMYE <= '1' after 5 ns;               
                        NEXT_STATE <= S4 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINRE | FARMRE for 2 sec
                        MAINRE <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;
                    end if;

        when S4 => if CYCLES = '2' then 
                        MAINRE <= '1' after 5 ns;
                        FARMGR <= '1' after 5 ns;           
                        NEXT_STATE <= S5 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINRE | FARMRE | FARMYE for 2 sec
                        MAINRE <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;
                        FARMYE <= '1' after 5 ns;
                    end if;

        when S5 => if CYCLES = '30' then 
                        MAINRE <= '1' after 5 ns;
                        FARMYE <= '1' after 5 ns;           
                        NEXT_STATE <= S6 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINRE | FARMGR for 30 sec
                        MAINRE <= '1' after 5 ns;
                        FARMGR <= '1' after 5 ns;   
                    end if; 

        when S6 => if CYCLES = '5' then 
                        MAINRE <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;           
                        NEXT_STATE <= S7 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINRE | FARMYE for 5 sec
                        MAINRE <= '1' after 5 ns;
                        FARMYE <= '1' after 5 ns;   
                    end if;

        when S7 => if CYCLES = '2' then 
                        MAINRE <= '1' after 5 ns;
                        MAINYE <= '1' after 5 ns;   
                        FARMRE <= '1' after 5 ns;       
                        NEXT_STATE <= S8 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINRE | FARMRE for 2 sec
                        MAINRE <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;       
                    end if;

        when S8 => if CYCLES = '2' then 
                        MAINGR <= '1' after 5 ns;
                        FARMRE <= '1' after 5 ns;           
                        NEXT_STATE <= S0 after 5 ns;
                        SCLR <= '1';
                    else                                -- MAINRE | MAINYE | FARMRE for 2 sec
                        MAINRE <= '1' after 5 ns;
                        MAINYE <= '1' after 5 ns;   
                        FARMRE <= '1' after 5 ns;       
                    end if;

end process AMP_KOMB;
end FUNKTION;

在尝试了许多不同的库之后，我找不到任何解决方案来修复此错误。我想这是因为错误的库或“=”运算符的错误使用造成的

以下是Modelsim的完整错误报告：

** Error: [...]/AMPSTR.vhdl(68): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(68): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(78): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(78): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(87): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(87): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(98): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(98): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(109): near "'": syntax error
** Error: [...]/AMPSTR.vhdl(114): near "else": expecting END or WHEN
** Error: [...]/AMPSTR.vhdl(117): near "if": expecting PROCESS

---

在<代码>中，如果周期='5'，则<代码>您预计会发生什么

循环

是一个无符号的循环。无论是

numeric\u std.unsigned

还是其他非标准库中的某种类型的unsigned，我无法判断，但我建议只使用

numeric\u std

库

在此上下文中，

'5'

是一个字符文本，而

5

是一个整数文本。根据错误消息，编译器显然无法在无符号和字符文字之间找到相等运算符

在

中，如果B1='1'，则
'1'
可以是字符文字或位文字；这两个表达式都是可见的，但只有一个是有意义的（定义了相等运算符），因此编译器对此表达式没有问题。
您缺少一个

    end case;

就在之前

end process AMP_KOMB;

您使用了错误的数字包，因为您使用的是位类型，所以您应该使用数字位。您不应该混合使用标准逻辑、无符号和数字逻辑：

library ieee;
-- use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.numeric_std.all;
use ieee.numeric_bit.all;

周期的数组长度为5，索引范围为
（4到0）
。与之一起使用的可接受的文本应为位字符串：

    when S1 => if CYCLES = '5' then 

应该是：

    when S1 => if CYCLES = "00101" then 

等（对每个地方的循环进行评估）。请注意，
'30'
不是字符文字，位字符串文字中的30是
“11110”

修复所有这些问题，并对VHDL设计规范进行分析和阐述。没有编写测试台，我没有模拟它

在看到Brian的答案后，值得指出的是，numeric_bit还有一个unsigned的类型声明以及相关的运算符。
David和Brian以前没有解决一些附加问题：


您的当前状态信号应该具有默认分配，因为它映射到寄存器
您的信号
SCLR
有多个驱动程序。只有一个进程应该为信号赋值。如果需要，则在这两个进程之间实施“通信协议”
您对状态名称使用的是枚举类型，而不是整数（这很好），因此请选择适当的枚举成员名称以增强代码的可读性：）
谢谢你，大卫！这对我帮助很大，解释很好，可以理解我到底做错了什么。也谢谢你，Brian，谢谢你的回答，David，我能够运行代码。
    when S1 => if CYCLES = "00101" then