vhdl乘法器 IEEE库； 使用IEEE.STD_LOGIC_1164.ALL； 实体Lab3_加法器为 端口（cin：标准_逻辑中； a：标准逻辑向量（3到0）； b：标准逻辑向量（3到0）； s：输出标准逻辑向量（3到0）； cout：输出标准逻辑）； 末端Lab3_加法器1； Lab3_加法器的结构是 信号c：标准逻辑向量（4到0）； 开始 c（0）

在VHDL中调用函数就像在c中调用函数一样——要么初始化常量、信号或变量，要么作为进程中的顺序语句。但现在这并不重要

但是你不能调用组件！这就好比在C++中调用一个对象——它绝对没有意义！ 在VHDL中，您可以实例化组件或（更简单！）实体，并使用信号互连它们的端口。这（非常非常粗糙）更像是用面向对象的语言声明对象和发送消息。这称为“结构VHDL”，通常出现在VHDL设计的顶层，用于创建和互连CPU、内存接口、FFT处理器等组件

鉴于你的实体

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

architecture Behavioral of Lab3_Adder1 is

    SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);

begin
    c(0) <= cin;
    s <= a XOR b XOR c (3 DOWNTO 0);
    c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
    cout <= c(4);
end Behavioral;

例如，我可以构建一个8位加法器，如下所示：

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

---

在VHDL中调用函数就像在C中调用函数一样——要么初始化常量、信号或变量，要么作为进程中的顺序语句。但现在这并不重要

但是你不能调用组件！这就好比在C++中调用一个对象——它绝对没有意义！ 在VHDL中，您可以实例化组件或（更简单！）实体，并使用信号互连它们的端口。这（非常非常粗糙）更像是用面向对象的语言声明对象和发送消息。这称为“结构VHDL”，通常出现在VHDL设计的顶层，用于创建和互连CPU、内存接口、FFT处理器等组件

鉴于你的实体

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

architecture Behavioral of Lab3_Adder1 is

    SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);

begin
    c(0) <= cin;
    s <= a XOR b XOR c (3 DOWNTO 0);
    c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
    cout <= c(4);
end Behavioral;

例如，我可以构建一个8位加法器，如下所示：

entity Lab3_Adder1 is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end Lab3_Adder1;

---

您可以定义VHDL函数，这些函数替代组合电路，并且可以在主VHDL代码中的任何地方调用，类似于C函数

您需要首先定义函数定义所在的包

=======myAdders.vhdl==============

entity Adder_8bit is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end Adder_8bit;

architecture Structural of Adder_8bit is

signal carry_int : std_logic;   -- between lower and upper halves

begin
-- We need to create and connect up two adders

LSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => cin,
           a  => a(3 downto 0),
           b  => b(3 downto 0),
           s  => s(3 downto 0),
           cout => carry_int
    );
MSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => carry_int,
           a  => a(7 downto 4),
           b  => b(7 downto 4),
           s  => s(7 downto 4),
           cout => cout
    );

end Structural;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

package myAdders is

function Lab3_Adder1( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;

end myAdders;

package body myAdders is


function Lab3_Adder1 ( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin

c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;


end myAdders;

=======topLevel.vhdl==============

entity Adder_8bit is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end Adder_8bit;

architecture Structural of Adder_8bit is

signal carry_int : std_logic;   -- between lower and upper halves

begin
-- We need to create and connect up two adders

LSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => cin,
           a  => a(3 downto 0),
           b  => b(3 downto 0),
           s  => s(3 downto 0),
           cout => carry_int
    );
MSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => carry_int,
           a  => a(7 downto 4),
           b  => b(7 downto 4),
           s  => s(7 downto 4),
           cout => cout
    );

end Structural;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

package myAdders is

function Lab3_Adder1( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;

end myAdders;

package body myAdders is


function Lab3_Adder1 ( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin

c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;


end myAdders;

IEEE库；
使用IEEE.std_logic_1164.all；
使用IEEE.std_logic_unsigned.all；
使用work.myAddres.all；
实体顶层是
港口（
cin：标准逻辑；
a：标准逻辑向量（3到0）；
b：标准逻辑向量（3到0）；
c：输出标准逻辑向量（3到0）
);
末端顶层；
顶层的架构是
信号进位：标准逻辑；
开始
carry您可以定义VHDL函数，这些函数替代组合电路，并且可以在主VHDL代码中的任何地方调用，类似于C函数

您需要首先定义函数定义所在的包

=======myAdders.vhdl==============

entity Adder_8bit is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end Adder_8bit;

architecture Structural of Adder_8bit is

signal carry_int : std_logic;   -- between lower and upper halves

begin
-- We need to create and connect up two adders

LSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => cin,
           a  => a(3 downto 0),
           b  => b(3 downto 0),
           s  => s(3 downto 0),
           cout => carry_int
    );
MSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => carry_int,
           a  => a(7 downto 4),
           b  => b(7 downto 4),
           s  => s(7 downto 4),
           cout => cout
    );

end Structural;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

package myAdders is

function Lab3_Adder1( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;

end myAdders;

package body myAdders is


function Lab3_Adder1 ( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin

c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;


end myAdders;

=======topLevel.vhdl==============

entity Adder_8bit is
    Port ( cin : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end Adder_8bit;

architecture Structural of Adder_8bit is

signal carry_int : std_logic;   -- between lower and upper halves

begin
-- We need to create and connect up two adders

LSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => cin,
           a  => a(3 downto 0),
           b  => b(3 downto 0),
           s  => s(3 downto 0),
           cout => carry_int
    );
MSB_adder : entity work.Lab3_Adder1
    Port Map( 
           cin => carry_int,
           a  => a(7 downto 4),
           b  => b(7 downto 4),
           s  => s(7 downto 4),
           cout => cout
    );

end Structural;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

package myAdders is

function Lab3_Adder1( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;

end myAdders;

package body myAdders is


function Lab3_Adder1 ( cin : in  STD_LOGIC;
a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in  STD_LOGIC_VECTOR (3 downto 0);
s : out  STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin

c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;


end myAdders;

IEEE库；
使用IEEE.std_logic_1164.all；
使用IEEE.std_logic_unsigned.all；
使用work.myAddres.all；
实体顶层是
港口（
cin：标准逻辑；
a：标准逻辑向量（3到0）；
b：标准逻辑向量（3到0）；
c：输出标准逻辑向量（3到0）
);
末端顶层；
顶层的架构是
信号进位：标准逻辑；
开始
携带