Compiler errors 用于在Verilog中打包和解包三维阵列的宏

我是Verilog的初学者，我想在代码中打包和解包3-D输入和输出，我为其定义了两个宏，如下所示：

`define PACK_3D(PK_WIDTH,PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST) \
genvar pk_idh; \
genvar pk_idd; \
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin \
  generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin \
      assign PK_DEST[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)] = PK_SRC[pk_idd][pk_idh][(PK_WIDTH)-1):0]; \
  end \
endgenerate \
end \
endgenerate



`define UNPACK_3D(PK_WIDTH, PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST) \
genvar pk_idh; \
genvar pk_idd; \
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin \
  generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin \
    assign PK_DEST[pk_idd][pk_idh][(PK_WIDTH)-1):0] = PK_SRC[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)]; \
  end \
  endgenerate \
end \
endgenerate

module add(clk, rst, g_input, e_input, o);
input clk,rst;   
localparam num=4;  
localparam h = 3;
localparam w = 3;
localparam d = 2;

input [2*num*h*w*d-1:0] g_input; 
input [2*num*h*w*d-1:0] e_input;  
output reg [2*num*h*w*d-1:0] o;

reg [2*num -1: 0] g_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] e_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] o_unpack[d-1:0][h-1:0][w-1:0];


`UNPACK_3D(w,h,d,g_input,g_unpack);
`UNPACK_3D(w,h,d,e_input,e_unpack);

integer i_d, i_h, i_w 

always@*   // always combinational block
  begin
    for (i_d = 0; i_d < d; i_d = i_d+1)
      begin
      for (i_h = 0; i_h < d; i_h = i_h+1)
        begin
        for (i_w = 0; i_w < d; i_w = i_w+1)
          begin
            o_unpack[i_d][i_h][i_w] = g_unpack[i_d][i_h][i_w] + e_unpack[i_d][i_h][i_w];
          end
        end
      end
  end

`PACK_3D(w,h,d,o_unpack,o);
endmodule

谁能帮忙解决这个问题？

---

谢谢。

您已经嵌套了

生成的

您应该只有一个
generate..endgenerate
与内部的两个
for
循环配对

此外，如果您在代码实例中声明了两次genvar（
genvar pk_idh；genvar pk_idd；
），即使您使它们在打包和解包之间有所不同，您也只能在每个模块中调用每个宏一次

我还建议您首先尝试不使用宏的代码。然后，当语法正确且代码正常工作时，尝试将其转换为宏。
谢谢，我将尝试您的建议并返回。您可以删除所有
generate
/
endgenerate
关键字。在Verilog-2001中有一些是可选的。
Error:  ./add.v:43: Syntax error at or near token 'generate'
    in macro "UNPACK_3D"
    called from file "./add.v" (line 43). (VER-294)
Error:  ./add.v:43: Syntax error at or near token '('
    in macro "UNPACK_3D"
    called from file "./add.v" (line 43). (VER-294)
Error:  ./add.v:44: Syntax error at or near token 'generate'
    in macro "UNPACK_3D"
    called from file "./add.v" (line 44). (VER-294)
Error:  ./add.v:44: Syntax error at or near token '('
    in macro "UNPACK_3D"
    called from file "./add.v" (line 44). (VER-294)
Error:  ./add.v:44: Syntax error at or near token '('
    in macro "UNPACK_3D"
    called from file "./add.v" (line 44). (VER-294)
Error:  ./add.v:48: Syntax error at or near token 'always'. (VER-294)
Error:  ./add.v:50: Syntax error at or near token ';'. (VER-294)
Error:  ./add.v:52: Syntax error at or near token ';'. (VER-294)
Error:  ./add.v:54: Syntax error at or near token ';'. (VER-294)
Error:  ./add.v:62: Syntax error at or near token 'generate'
    in macro "PACK_3D"
    called from file "./add.v" (line 62). (VER-294)
Error:  ./add.v:62: Syntax error at or near token '('
    in macro "PACK_3D"
    called from file "./add.v" (line 62). (VER-294)
Error:  ./add.v:62: Syntax error at or near token '('
    in macro "PACK_3D"
    called from file "./add.v" (line 62). (VER-294)
*** Presto compilation terminated with 12 errors. ***