Vector 如何在VHDL中测试矢量多路复用器的所有情况？

这是我的第一个VHDL代码，我有一个多路复用器（两个输入，一个选择位），它有8位向量输入。如何编写生成所有可能向量的测试函数

library IEEE;
use IEEE.std_logic_1164.all;

entity mux is
port(
    in0, in1: in std_logic_vector(7 downto 0);
    sel: in std_logic;
    out0: out std_logic_vector(7 downto 0);
end mux;

architecture dataflow of mux is
begin
    out0<=in1 when sel='1'
    else in0;
end dataflow;

IEEE库；
使用IEEE.std_logic_1164.all；
实体多路复用器是
港口(
in0，in1:in标准逻辑向量（7到0）；
sel：标准逻辑中；
out0：out标准逻辑矢量（7到0）；
端多路复用器；
mux的体系结构数据流是
开始
out0可以使用类似的方法：

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is --empty
end testbench;

architecture tb of testbench is

signal tb_sel: std_logic;
signal tb_in0, tb_in1, tb_out0: std_logic_vector(7 downto 0);

begin
-- Connect DuT

  DuT: entity work.mux port map(tb_in0, tb_in1, tb_sel, tb_out0);

process
begin
    -- Done: Test all possibilities

    for sel in 0 to 1 loop
      for in0 in 0 to 2 ** tb_in0'length - 1 loop
        for in1 in 0 to 2 ** tb_in1'length - 1 loop
          -- Make stimuli
          if sel = 0 then
            tb_sel <= '0';
          else
            tb_sel <= '1';
          end if;
          tb_in0 <= std_logic_vector(to_unsigned(in0, tb_in0'length));
          tb_in1 <= std_logic_vector(to_unsigned(in1, tb_in1'length));
          -- Wait for output, also to ease viewing in waveforms
          wait for 10 ns;
          -- Test output
          if sel = 0 then
            assert tb_out0 = tb_in0 report "Wrong out0 output value for selected in0 input" severity error;
          else
            assert tb_out0 = tb_in1 report "Wrong out0 output value for selected in1 input" severity error;
          end if;
        end loop;
      end loop;
    end loop;

    report "OK   (not actual failure)" severity FAILURE;
    wait;

    end process;
end tb;

IEEE库；
使用IEEE.std_logic_1164.all；
使用ieee.numeric_std.all；
实体testbench为空
端部试验台；
测试台的体系结构是
信号tb_sel:std_逻辑；
信号tb_in0，tb_in1，tb_out0:std_逻辑向量（7到0）；
开始
--连接DuT
DuT:entity work.mux端口映射（tb_in0、tb_in1、tb_sel、tb_out0）；
过程
开始
--完成：测试所有可能性
对于0到1循环中的sel
对于0到2英寸的in0**tb_in0'长度-1圈
对于1英寸0到2英寸**tb_英寸1'长度-1循环
--刺激
如果sel=0，则
特布塞尔
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is --empty
end testbench;

architecture tb of testbench is

signal tb_sel: std_logic;
signal tb_in0, tb_in1, tb_out0: std_logic_vector(7 downto 0);

begin
-- Connect DuT

  DuT: entity work.mux port map(tb_in0, tb_in1, tb_sel, tb_out0);

process
begin
    -- Done: Test all possibilities

    for sel in 0 to 1 loop
      for in0 in 0 to 2 ** tb_in0'length - 1 loop
        for in1 in 0 to 2 ** tb_in1'length - 1 loop
          -- Make stimuli
          if sel = 0 then
            tb_sel <= '0';
          else
            tb_sel <= '1';
          end if;
          tb_in0 <= std_logic_vector(to_unsigned(in0, tb_in0'length));
          tb_in1 <= std_logic_vector(to_unsigned(in1, tb_in1'length));
          -- Wait for output, also to ease viewing in waveforms
          wait for 10 ns;
          -- Test output
          if sel = 0 then
            assert tb_out0 = tb_in0 report "Wrong out0 output value for selected in0 input" severity error;
          else
            assert tb_out0 = tb_in1 report "Wrong out0 output value for selected in1 input" severity error;
          end if;
        end loop;
      end loop;
    end loop;

    report "OK   (not actual failure)" severity FAILURE;
    wait;

    end process;
end tb;