我的Verilog输出测试结果的值为x
这是我第一次使用Verilog，我不明白为什么我的输出总是给我x值，我的代码非常简单，我怀疑它需要很多解释我的Verilog输出测试结果的值为x,verilog,Verilog,这是我第一次使用Verilog，我不明白为什么我的输出总是给我x值，我的代码非常简单，我怀疑它需要很多解释 module Network_Router (P, Q, R, S, Output); input P, Q, R, S; output Output; wire Output; reg and1, and2, and3, and4, and5, and6, or1, or2, or3, or4, or5; initial begin and1 = P & Q; and2 = Q
module Network_Router (P, Q, R, S, Output);
input P, Q, R, S;
output Output;
wire Output;
reg and1, and2, and3, and4, and5, and6, or1, or2, or3, or4, or5;
initial
begin
and1 = P & Q;
and2 = Q & R;
or1 = and1 | and2;
and3 = P & R;
and4 = S & R;
or2 = and3 | and4;
or3 = or1 | or2;
and5 = Q & S;
and6 = P & S;
or4 = and5 | and6;
or5 = or3 | or4;
end
assign Output = or5;
endmodule
`include "netRouter.v"
module netRouter_tb;
reg P, Q, R, S;
wire Output;
Network_Router test(P, Q, R, S, Output);
initial
begin
//Dump results of the simulation to netRouter.vcd
$dumpfile("netRouter.vcd");
$dumpvars;
P <= 0; Q <= 0; R <= 0; S <= 0;
#5
P <= 0; Q <= 0; R <= 0; S <= 1;
#5
P <= 0; Q <= 0; R <= 1; S <= 0;
#5
P <= 0; Q <= 0; R <= 1; S <= 1;
#5
P <= 0; Q <= 1; R <= 0; S <= 0;
#5
P <= 0; Q <= 1; R <= 0; S <= 1;
#5
P <= 0; Q <= 1; R <= 1; S <= 0;
#5
P <= 0; Q <= 1; R <= 1; S <= 1;
#5
P <= 1; Q <= 0; R <= 0; S <= 0;
#5
P <= 1; Q <= 0; R <= 0; S <= 1;
#5
P <= 1; Q <= 0; R <= 1; S <= 0;
#5
P <= 1; Q <= 0; R <= 1; S <= 1;
#5
P <= 1; Q <= 1; R <= 0; S <= 0;
#5
P <= 1; Q <= 1; R <= 0; S <= 1;
#5
P <= 1; Q <= 1; R <= 1; S <= 0;
#5
P <= 1; Q <= 1; R <= 1; S <= 1;
end
initial
begin
$monitor("time=%4d: %b %b %b %b : Output = %b",$time,P, Q, R, S, Output);
end
endmodule
`包括“netRouter.v”
网络路由器模块；
注册P、Q、R、S；
导线输出；
网络路由器测试（P、Q、R、S、输出）；
首字母
开始
//将模拟结果转储到netRouter.vcd
$dumpfile（“netRouter.vcd”）；
$dumpvars；
P网络路由器模块中有一个
首字母。
将其替换为始终@（*）
当代码开始时，该初始值执行一次，然后再也不会执行。当代码启动时，所有的注册表值都是x