Verilog计数器始终块不工作_Verilog

Verilog计数器始终块不工作

verilog

Verilog计数器始终块不工作,verilog,Verilog,我对以下代码的PC部分有问题。它应该从0开始计数，但在我运行testbench文件时不计数。我和TA谈过，不明白为什么测试台文件没有计算PC寄存器。当我运行testbench文件时，PC以某种方式抛出一些垃圾值。有人能帮我弄清楚为什么它不起作用吗 # 0TEST MY DESIGN # 0Address bus: x, STR Data : x, LDR Data :

我对以下代码的

PC

部分有问题。它应该从0开始计数，但在我运行testbench文件时不计数。我和TA谈过，不明白为什么测试台文件没有计算PC寄存器。当我运行testbench文件时，

PC

以某种方式抛出一些垃圾值。有人能帮我弄清楚为什么它不起作用吗

#                    0TEST MY DESIGN
#                    0Address bus:          x, STR Data :          x, LDR Data :          x, Read: x, Write: x, PC:          x, Reset is x
#                    2Address bus:          x, STR Data :          x, LDR Data :          x, Read: 0, Write: 0, PC:          x, Reset is 0
#                    6Address bus:          x, STR Data :          x, LDR Data :          x, Read: 0, Write: 0, PC:          x, Reset is 1
#                   11Address bus:         10, STR Data :          x, LDR Data :          7, Read: 1, Write: 0, PC:          x, Reset is 1
#                   21Address bus:          7, STR Data :          2, LDR Data :          7, Read: 0, Write: 1, PC:          x, Reset is 1
#                   31Address bus:         10, STR Data :          2, LDR Data :          9, Read: 1, Write: 0, PC:          x, Reset is 1
#                   41Address bus:          9, STR Data :          7, LDR Data :          9, Read: 0, Write: 1, PC:          x, Reset is 1
#                   51Address bus:          x, STR Data :          7, LDR Data :          9, Read: 0, Write: 0, PC:          x, Reset is 1

代码：

下面的模块是上述Verilog文件的测试台文件

module MemoryContro_t;

reg [31:0] Result_t,source1_t,source2_t,DataBus_L_t;
reg [3:0] opcode_t;
reg Clk_t,Reset_t;
wire LDR_EN_t, Address_EN_t;
wire [31:0]PC_t, AddBus_t,DataBus_S_t,LDRin_t;
wire R_t,W_t;

initial begin
$display($time,"TEST MY DESIGN");
#2 Result_t=0; source1_t=0; source2_t=0; DataBus_L_t = 0; opcode_t=0; Reset_t = 0; 
#4 Reset_t = 1;
#5 Result_t=0; source1_t=10; source2_t=5; DataBus_L_t = 7; opcode_t=4'b1110;  // LDR Test ,LDR Data initialized
#10 Result_t=0; source1_t=7; source2_t=2; DataBus_L_t = 6; opcode_t=4'b1101;  // STR Test ,STR Data initialized 
#10 Result_t=0; source1_t=10; source2_t=5; DataBus_L_t = 9; opcode_t=4'b1110; // LDR Test ,LDR Data overwritten
#10 Result_t=0; source1_t=9; source2_t=7; DataBus_L_t = 10; opcode_t=4'b1101; // STR Test ,STR Data overwritten
#10 Result_t=0; source1_t=9; source2_t=7; DataBus_L_t = 10; opcode_t=!4'b1101&&4'b1110; // PC TEST

end

always #5 Clk_t=~Clk_t;
initial begin
$monitor($time,"Address bus: %d, STR Data : %d, LDR Data : %d, Read: %d, Write: %d, PC: %d, Reset is %d", AddBus_t, DataBus_S_t,LDRin_t,R_t,W_t,PC_t, Reset_t);
end

MemoryControl MUT (.Clk(Clk_t),.PC(PC_t),.Reset(Reset_t),.Result(Result_t),.source1(source1_t),.source2(source2_t),.opcode(opcode_t),
.LDR_EN(LDR_EN_t),.Address_EN(Address_EN_t),.AddBus(AddBus_t),.DataBus_L(DataBus_L_t),.DataBus_S(DataBus_S_t),.LDRin(LDRin_t),.R(R_t),.W(W_t));
endmodule

您需要在测试台模块中初始化时钟信号。您将其声明为

reg

，这意味着其初始值为X（未知）

它在整个模拟过程中保持为X，这意味着

PC

值永远不会增加，因为

始终@（posedge Clk）

不会触发

如果您没有使用波形调试仿真，则应该。当我观察波浪时，我立刻注意到了这个问题

时钟没有初始值，您可以使用以下样式进行设置： reg Clk_t=1'b0

DUT中的复位处于低激活状态，因此在TB中，应将结果设置为0，然后将其设置为1

你的第二点不正确。运行模拟并查看波形。复位信号在时间2为0，然后在时间6设置为1，并在整个模拟中保持为1。

结果\u t

信号不是重置信号（

重置\u t

）。

module MemoryContro_t;

reg [31:0] Result_t,source1_t,source2_t,DataBus_L_t;
reg [3:0] opcode_t;
reg Clk_t,Reset_t;
wire LDR_EN_t, Address_EN_t;
wire [31:0]PC_t, AddBus_t,DataBus_S_t,LDRin_t;
wire R_t,W_t;

initial begin
$display($time,"TEST MY DESIGN");
#2 Result_t=0; source1_t=0; source2_t=0; DataBus_L_t = 0; opcode_t=0; Reset_t = 0; 
#4 Reset_t = 1;
#5 Result_t=0; source1_t=10; source2_t=5; DataBus_L_t = 7; opcode_t=4'b1110;  // LDR Test ,LDR Data initialized
#10 Result_t=0; source1_t=7; source2_t=2; DataBus_L_t = 6; opcode_t=4'b1101;  // STR Test ,STR Data initialized 
#10 Result_t=0; source1_t=10; source2_t=5; DataBus_L_t = 9; opcode_t=4'b1110; // LDR Test ,LDR Data overwritten
#10 Result_t=0; source1_t=9; source2_t=7; DataBus_L_t = 10; opcode_t=4'b1101; // STR Test ,STR Data overwritten
#10 Result_t=0; source1_t=9; source2_t=7; DataBus_L_t = 10; opcode_t=!4'b1101&&4'b1110; // PC TEST

end

always #5 Clk_t=~Clk_t;
initial begin
$monitor($time,"Address bus: %d, STR Data : %d, LDR Data : %d, Read: %d, Write: %d, PC: %d, Reset is %d", AddBus_t, DataBus_S_t,LDRin_t,R_t,W_t,PC_t, Reset_t);
end

MemoryControl MUT (.Clk(Clk_t),.PC(PC_t),.Reset(Reset_t),.Result(Result_t),.source1(source1_t),.source2(source2_t),.opcode(opcode_t),
.LDR_EN(LDR_EN_t),.Address_EN(Address_EN_t),.AddBus(AddBus_t),.DataBus_L(DataBus_L_t),.DataBus_S(DataBus_S_t),.LDRin(LDRin_t),.R(R_t),.W(W_t));
endmodule

initial Clk_t = 0;