Always块中存在多个Verilog错误_Verilog

Always块中存在多个Verilog错误

verilog

Always块中存在多个Verilog错误,verilog,Verilog,我正在尝试用Verilog创建一个算术逻辑单元。我是个新手，所以如果我对事情的运作方式有点无知，请原谅我。在尝试编译我的项目时，我遇到了几个错误： Error (10170): Verilog HDL syntax error at alu.v(45) near text: â. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPG

我正在尝试用Verilog创建一个算术逻辑单元。我是个新手，所以如果我对事情的运作方式有点无知，请原谅我。在尝试编译我的项目时，我遇到了几个错误：

Error (10170): Verilog HDL syntax error at alu.v(45) near text: â. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at alu.v(45) near text: "â";  expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at alu.v(45) near text: . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at alu.v(45) near text: . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10149): Verilog HDL Declaration error at alu.v(49): identifier "addA2" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at alu.v(49): identifier "addA1" is already declared in the present scope
Error (10170): Verilog HDL syntax error at alu.v(49) near text: "}";  expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10149): Verilog HDL Declaration error at alu.v(51): identifier "ab2" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at alu.v(51): identifier "ab1" is already declared in the present scope
Error (10170): Verilog HDL syntax error at alu.v(51) near text: "}";  expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10149): Verilog HDL Declaration error at alu.v(53): identifier "abvo" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at alu.v(53): identifier "abv" is already declared in the present scope
Error (10170): Verilog HDL syntax error at alu.v(53) near text: "}";  expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at alu.v(66) near text: ")";  expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "subALU" at alu.v(24) due to previous errors
Error (10112): Ignored design unit "rippleCarryAdder" at alu.v(75) due to previous errors
Error (10112): Ignored design unit "fullAdder" at alu.v(116) due to previous errors
Error (10112): Ignored design unit "sevenSegDecoder" at alu.v(128) due to previous errors

我有点不知所措，不知道有没有人有什么见解。以下是模块抛出错误：

module subALU(A, B, func, ALUout);
    input [3:0] A;
    input [3:0] B;
    input [2:0] func;
    output [7:0] ALUout;

    //A+1
    reg [3:0] addA1;
    reg addA2;
    rippleCarryAdder add1(.A(A), .B(4'b0001), .cin(0), .s(addA1), .cout(addA2));

    //A+B
    reg [3:0] ab1;
    reg ab2;
    rippleCarryAdder add2(.A(A), .B(B), .cin(0), .s(ab1), .cout(ab2));

    //A+B using Verilog
    reg [3:0] abv;
    reg abvo;
    fourBitAdd add3(.X(A), .Y(B), .C(abv), .overflow(abvo));

    always @(∗)
    begin
        case (func)
            //A + 1
            3'b000: ALUout[7:0] = {3'b000, addA2, addA1};
            //A + B (Using rippleCarryAdder)
            3'b001: ALUout = {3'b000, ab2, ab1};
            //A + B (Using Verilog arithmetic)
            3'b010: ALUout = {3'b000, abvo, abv};
            //A XOR B in lower 4 bits, A OR B in higher 4
            3'b011: ALUout = {A | B, A ^ B};
            //A and B reduction OR
            3'b100: ALUout = {7'b0000000, |(A|B)};
            //A in leftmost 4 bits, B in rightmost 4 bits 
            3'b101: ALUout = {A, B};
            //Display 0
            default: ALUout = 8'b00000000
        endcase
    end
endmodule

如果有人能让我知道我做错了什么，我会非常感激

谢谢

这样写吧

module subALU(A, B, func, ALUout);
input [3:0] A;
input [3:0] B;
input [2:0] func;
output reg[7:0] ALUout;

//A+1
wire [3:0] addA1;
wire addA2;
rippleCarryAdder add1(.A(A), .B(4'b0001), .cin(0), .s(addA1), .cout(addA2));

//A+B
wire [3:0] ab1;
wire ab2;
rippleCarryAdder add2(.A(A), .B(B), .cin(0), .s(ab1), .cout(ab2));

//A+B using Verilog
wire [3:0] abv;
wire abvo;
fourBitAdd add3(.X(A), .Y(B), .C(abv), .overflow(abvo));

always @(∗)
begin
    case (func)
        //A + 1
        3'b000: ALUout[7:0] = {3'b000, addA2, addA1};
        //A + B (Using rippleCarryAdder)
        3'b001: ALUout = {3'b000, ab2, ab1};
        //A + B (Using Verilog arithmetic)
        3'b010: ALUout = {3'b000, abvo, abv};
        //A XOR B in lower 4 bits, A OR B in higher 4
        3'b011: ALUout = {A | B, A ^ B};
        //A and B reduction OR
        3'b100: ALUout = {7'b0000000, |(A|B)};
        //A in leftmost 4 bits, B in rightmost 4 bits 
        3'b101: ALUout = {A, B};
        //Display 0
        default: ALUout = 8'b00000000
    endcase
end

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