高阻抗信号未进入测试台[VHDL]
首先，我不熟悉VHDL，我试图创建一个RAM模型（或类似的东西）。该模型运行良好，我开始构建我的测试台，但它不再现从原始模型生成的信号文件的行为。主要问题是，高阻抗信号“**Z”变为“U”（未定义），在重置信号之后，值（X“0000”*）变为“*X”。**”（未知）.我在测试台上有3个主要测试，标记为Test_N，但第一个测试，最后一个测试由于上述错误而失败。因此，带有Test_1和Test_3的行被注释。下面是RAM.vhd和RAM_TB.vhd的代码，以及两个测试它们的屏幕截图 RAM.vhd高阻抗信号未进入测试台[VHDL],vhdl,waveform,active-hdl,Vhdl,Waveform,Active Hdl,首先，我不熟悉VHDL，我试图创建一个RAM模型（或类似的东西）。该模型运行良好，我开始构建我的测试台，但它不再现从原始模型生成的信号文件的行为。主要问题是，高阻抗信号“**Z”变为“U”（未定义），在重置信号之后，值（X“0000”*）变为“*X”。**”（未知）.我在测试台上有3个主要测试，标记为Test_N，但第一个测试，最后一个测试由于上述错误而失败。因此，带有Test_1和Test_3的行被注释。下面是RAM.vhd和RAM_TB.vhd的代码，以及两个测试它们的屏幕截图 RAM.vh
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM is
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end RAM;
architecture BEH of RAM is
type MEM2KX16 is array(0 to 2047) of std_logic_vector(AD'range);
constant RAM_init : MEM2KX16 := (X"0000", others=>X"0000"); -- initial memory state
signal do : std_logic_vector(AD'range); -- signal for data output
signal addr : std_logic_vector(10 downto 0); -- 2047 = 0111 1111 1111, 11 bits needed
signal addri : natural;
signal RAM_out : MEM2KX16; -- For debug purposes
begin
RG_ADDR : process (CLK, R)
begin
if (R = '1') then
addr <= "00000000000"; -- Reset address
elsif rising_edge(CLK) and AE = '1' then
addr <= AD(10 downto 0); -- Receive address
end if;
end process;
RAM2K : process (CLK, addr, addri)
variable RAM : MEM2KX16 := RAM_init;
begin
addri <= to_integer(unsigned(addr(10 downto 0)));
if rising_edge(CLK) then
if (WR = '1') then -- Write to memory
RAM(addri) := AD(15 downto 0);
end if;
if (R = '1') then -- Reset memory
do <= X"0000";
else
do <= RAM(addri); -- Return data from memory
end if;
end if;
RAM_out <= RAM; -- For debug purposes
end process;
TRI : AD <= do when (OE = '1') -- Three-state buffer
else "ZZZZZZZZZZZZZZZZ";
end architecture;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM_TB is
end entity;
architecture RAM_TB_arch of RAM_TB is
component RAM
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end component;
constant T : time := 20 ns;
signal CLK_TB, R_TB, WR_TB, AE_TB, OE_TB : std_logic;
signal AD_TB : std_logic_vector(15 downto 0);
begin
DUT : RAM port map (CLK_TB, R_TB, WR_TB, AE_TB, OE_TB, AD_TB);
process
begin
CLK_TB <= '0';
wait for T/2;
CLK_TB <= '1';
wait for T/2;
end process;
STIMULUS : process
variable value : std_logic_vector(AD_TB'range) := X"FFFF";
variable addr : std_logic_vector(AD_TB'range) := X"0004";
begin
-- Test ZZZZ output of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '0'; -- No address
OE_TB <= '0'; -- No output
wait for 2*T;
--Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
-- Test input of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '1'; -- Read address
OE_TB <= '0'; -- No output
AD_TB <= addr; -- Address RAM(4)
wait for T;
WR_TB <= '1'; -- Write
AE_TB <= '0'; -- Do not read address
AD_TB <= value; -- Data to write
wait for T;
-- Test output of AD
WR_TB <= '0'; -- No write
OE_TB <= '1'; -- Output data from RAM
wait for T;
Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
-- Test Reset
R_TB <= '1'; -- Reset
wait for T;
--Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
wait;
end process;
end architecture;
signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM_TB is
end entity;
architecture RAM_TB_arch of RAM_TB is
component RAM
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end component;
constant T : time := 20 ns;
signal CLK_TB, R_TB, WR_TB, AE_TB, OE_TB : std_logic;
signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
begin
DUT : RAM port map (CLK_TB, R_TB, WR_TB, AE_TB, OE_TB, AD_TB);
process
begin
CLK_TB <= '0';
wait for T/2;
CLK_TB <= '1';
wait for T/2;
end process;
STIMULUS : process
variable value : std_logic_vector(AD_TB'range) := X"FFFF";
variable addr : std_logic_vector(AD_TB'range) := X"0004";
begin
-- Test ZZZZ output of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '0'; -- No address
OE_TB <= '0'; -- No output
wait for 2*T;
Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
-- Test input of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '1'; -- Read address
OE_TB <= '0'; -- No output
AD_TB <= addr; -- Address RAM(4)
wait for T;
WR_TB <= '1'; -- Write
AE_TB <= '0'; -- Do not read address
AD_TB <= value; -- Data to write
wait for T;
-- Test output of AD
AD_TB <= "ZZZZZZZZZZZZZZZZ";
WR_TB <= '0'; -- No write
OE_TB <= '1'; -- Output data from RAM
wait for T;
Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
-- Test Reset
wait for T;
R_TB <= '1'; -- Reset
AD_TB <= "ZZZZZZZZZZZZZZZZ";
wait for T;
Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
wait;
end process;
end architecture;
R_TB <= '1'; -- Reset
AD_TB <= "ZZZZZZZZZZZZZZZZ";
wait for T;
R_TB在@BrianDrummond和@Tricky评论的指导下，我可以发布问题的答案。问题的原因和解决方法可以在问题下方的评论中找到
RAM_TB.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM is
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end RAM;
architecture BEH of RAM is
type MEM2KX16 is array(0 to 2047) of std_logic_vector(AD'range);
constant RAM_init : MEM2KX16 := (X"0000", others=>X"0000"); -- initial memory state
signal do : std_logic_vector(AD'range); -- signal for data output
signal addr : std_logic_vector(10 downto 0); -- 2047 = 0111 1111 1111, 11 bits needed
signal addri : natural;
signal RAM_out : MEM2KX16; -- For debug purposes
begin
RG_ADDR : process (CLK, R)
begin
if (R = '1') then
addr <= "00000000000"; -- Reset address
elsif rising_edge(CLK) and AE = '1' then
addr <= AD(10 downto 0); -- Receive address
end if;
end process;
RAM2K : process (CLK, addr, addri)
variable RAM : MEM2KX16 := RAM_init;
begin
addri <= to_integer(unsigned(addr(10 downto 0)));
if rising_edge(CLK) then
if (WR = '1') then -- Write to memory
RAM(addri) := AD(15 downto 0);
end if;
if (R = '1') then -- Reset memory
do <= X"0000";
else
do <= RAM(addri); -- Return data from memory
end if;
end if;
RAM_out <= RAM; -- For debug purposes
end process;
TRI : AD <= do when (OE = '1') -- Three-state buffer
else "ZZZZZZZZZZZZZZZZ";
end architecture;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM_TB is
end entity;
architecture RAM_TB_arch of RAM_TB is
component RAM
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end component;
constant T : time := 20 ns;
signal CLK_TB, R_TB, WR_TB, AE_TB, OE_TB : std_logic;
signal AD_TB : std_logic_vector(15 downto 0);
begin
DUT : RAM port map (CLK_TB, R_TB, WR_TB, AE_TB, OE_TB, AD_TB);
process
begin
CLK_TB <= '0';
wait for T/2;
CLK_TB <= '1';
wait for T/2;
end process;
STIMULUS : process
variable value : std_logic_vector(AD_TB'range) := X"FFFF";
variable addr : std_logic_vector(AD_TB'range) := X"0004";
begin
-- Test ZZZZ output of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '0'; -- No address
OE_TB <= '0'; -- No output
wait for 2*T;
--Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
-- Test input of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '1'; -- Read address
OE_TB <= '0'; -- No output
AD_TB <= addr; -- Address RAM(4)
wait for T;
WR_TB <= '1'; -- Write
AE_TB <= '0'; -- Do not read address
AD_TB <= value; -- Data to write
wait for T;
-- Test output of AD
WR_TB <= '0'; -- No write
OE_TB <= '1'; -- Output data from RAM
wait for T;
Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
-- Test Reset
R_TB <= '1'; -- Reset
wait for T;
--Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
wait;
end process;
end architecture;
signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM_TB is
end entity;
architecture RAM_TB_arch of RAM_TB is
component RAM
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end component;
constant T : time := 20 ns;
signal CLK_TB, R_TB, WR_TB, AE_TB, OE_TB : std_logic;
signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
begin
DUT : RAM port map (CLK_TB, R_TB, WR_TB, AE_TB, OE_TB, AD_TB);
process
begin
CLK_TB <= '0';
wait for T/2;
CLK_TB <= '1';
wait for T/2;
end process;
STIMULUS : process
variable value : std_logic_vector(AD_TB'range) := X"FFFF";
variable addr : std_logic_vector(AD_TB'range) := X"0004";
begin
-- Test ZZZZ output of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '0'; -- No address
OE_TB <= '0'; -- No output
wait for 2*T;
Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
-- Test input of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '1'; -- Read address
OE_TB <= '0'; -- No output
AD_TB <= addr; -- Address RAM(4)
wait for T;
WR_TB <= '1'; -- Write
AE_TB <= '0'; -- Do not read address
AD_TB <= value; -- Data to write
wait for T;
-- Test output of AD
AD_TB <= "ZZZZZZZZZZZZZZZZ";
WR_TB <= '0'; -- No write
OE_TB <= '1'; -- Output data from RAM
wait for T;
Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
-- Test Reset
wait for T;
R_TB <= '1'; -- Reset
AD_TB <= "ZZZZZZZZZZZZZZZZ";
wait for T;
Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
wait;
end process;
end architecture;
IEEE库；
使用IEEE.std_logic_1164.all；
使用IEEE.numeric_std.all；
实体RAM_TB是
终端实体；
RAM_TB的体系结构RAM_TB_拱是
组件RAM
端口（时钟：标准_逻辑中——时钟
R：在标准逻辑中；--复位
WR：在标准_逻辑中；--写入
AE：在标准逻辑中；--地址保存在temp中。
OE：在std_逻辑中；--关于输出字的信号
AD:inout标准逻辑向量（15到0）；--输出地址（11位地址）/输入数据（16位数据）
端部元件；
常数T：时间：=20纳秒；
信号CLK_TB、R_TB、WR_TB、AE_TB、OE_TB:std_逻辑；
信号AD_TB:std_逻辑_向量（15到0）：=（其他=>'Z'）；
开始
DUT:RAM端口图（CLK_TB、R_TB、WR_TB、AE_TB、OE_TB、AD_TB）；
过程
开始
CLK_TB测试台：信号AD_TB:std_逻辑_向量（15到0）；
默认情况下初始化为“U”。并且“Z”和“U”解析为“U”…在声明中添加一个初始化器子句到（其他=>'Z'）
。@BrianDrummond，您的修复程序部分解决了“U”问题，但“X”问题仍保留在上一次测试中。当您尝试读取内存时，检查是否有任何其他因素驱动该信号。在测试台上，您将AD_TB
驱动到x“FFFF”
但是，当ram试图驱动输出时，这会保留在总线上。当您试图读取数据时，需要将AD_TB
设置为others=>'Z'
ram@Tricky，哦，那是拼图的最后一块了）谢谢你的帮助！