如何移除vhdl中的锁存器以及RTL_ROM的用途？
下面的代码是一个简单的16位加法器（只使用一个四位加法器）。我试着避开所有的门闩。但我无法移除图像中高亮显示的闩锁（sum\u 16\u temp）。谁能帮我避开这个门闩吗。如果有人能帮助我理解RTL\u ROM（next\u state\u i）的用途，我将不胜感激如何移除vhdl中的锁存器以及RTL_ROM的用途？,vhdl,vlsi,Vhdl,Vlsi,下面的代码是一个简单的16位加法器（只使用一个四位加法器）。我试着避开所有的门闩。但我无法移除图像中高亮显示的闩锁（sum\u 16\u temp）。谁能帮我避开这个门闩吗。如果有人能帮助我理解RTL\u ROM（next\u state\u i）的用途，我将不胜感激 IEEE库； 使用IEEE.STD_LOGIC_1164.ALL； 实体十六位加法器是 端口（a_16：标准逻辑向量（15到0）； b_16：标准逻辑向量（15到0）； 进位逻辑单元16：标准逻辑单元； clk：标准逻辑中； 重置
IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
实体十六位加法器是
端口（a_16：标准逻辑向量（15到0）；
b_16：标准逻辑向量（15到0）；
进位逻辑单元16：标准逻辑单元；
clk：标准逻辑中；
重置_16：在标准_逻辑中；
完成添加：输出标准逻辑；
求和16：输出标准逻辑向量（15到0）；
执行（16：执行标准逻辑）；
结束十六位加法器；
介绍了16位加法器的结构
------------------信号声明------------------
信号和16温度：标准逻辑向量（15到0）：=x“0000”——临时款项登记册
信号执行温度：标准逻辑；——携带临时登记簿
类型状态_类型为（s0、s1、s2、s3、s4）；——国家；
信号下一个_状态，状态：状态_类型；
信号a_4，b_4，和4:STD_逻辑_向量（3到0）：=x“0”——4位元件输入的温度
信号进位输入4，进位输出4，完成温度：标准逻辑：='0'；
-------信号结束声明-------
------组件声明-------------
组件四位加法器是
端口（a：标准逻辑向量（3到0）；
b：标准逻辑向量（3到0）；
进位：在标准逻辑中；
求和4：输出标准逻辑向量（3到0）；
执行：执行标准逻辑）；
端部元件四位加法器；
------组件结束声明--------
开始
四位加法器1：四位加法器端口映射（a_4，b_4，进位在4，求和在4，进位在4）；
触发器进程：进程（复位16，时钟）
开始
如果重置_16='1'，则
sum_16我不愿意在没有答案的情况下给出问题的答案。没有办法知道是否还有其他问题
library ieee;
use ieee.std_logic_1164.all;
entity sixteen_bit_adder is
port (
a_16: in std_logic_vector (15 downto 0);
b_16: in std_logic_vector (15 downto 0);
carry_in_16: in std_logic;
clk: in std_logic;
reset_16: in std_logic;
done_addition: out std_logic;
sum_16: out std_logic_vector (15 downto 0);
carry_out_16: out std_logic
);
end entity sixteen_bit_adder;
architecture structural of sixteen_bit_adder is
-- signal sum_16_temp: std_logic_vector (15 downto 0) := x"0000";
signal carry_out_temp: std_logic;
type state_type is (s0,s1,s2,s3,s4);
signal next_state, state: state_type;
signal a_4, b_4, sum_4: std_logic_vector (3 downto 0) := x"0";
signal carry_in_4,
carry_out_4,
done_temp: std_logic := '0';
component four_bit_adder is
port (
a: in std_logic_vector (3 downto 0);
b: in std_logic_vector (3 downto 0);
carry_in: in std_logic;
sum_4: out std_logic_vector (3 downto 0);
carry_out: out std_logic
);
end component four_bit_adder;
begin
four_bit_adder1:
four_bit_adder
port map (a_4, b_4, carry_in_4, sum_4, carry_out_4);
flopping_process:
process (reset_16, clk)
begin
if reset_16 = '1' then
sum_16 <= x"0000";
carry_out_16 <= '0';
state <= s0;
done_addition <= '0';
elsif rising_edge(clk) then
case state is
when s0 =>
sum_16(3 downto 0) <= sum_4;
when s1 =>
sum_16(7 downto 4) <= sum_4;
when s2 =>
sum_16(11 downto 8) <= sum_4;
when s3 =>
sum_16(15 downto 12) <= sum_4;
when others =>
end case;
-- sum_16 <= sum_16_temp;
carry_out_16 <= carry_out_temp;
state <= next_state;
done_addition <= done_temp;
end if;
end process;
state_machine:
process (state, reset_16, a_16, b_16, carry_in_16, carry_in_4)
begin
if reset_16 = '0' then
case state is
when s0 =>
a_4 <= a_16(3 downto 0);
b_4 <= b_16(3 downto 0);
carry_in_4 <= carry_in_16;
next_state <= s1;
-- sum_16_temp(3 downto 0) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s1 =>
a_4 <= a_16(7 downto 4);
b_4 <= b_16(7 downto 4);
carry_in_4 <= carry_out_4;
-- sum_16_temp(3 downto 0) <= sum_4;
next_state <= s2;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s2 =>
a_4 <= a_16(11 downto 8);
b_4 <= b_16(11 downto 8);
carry_in_4 <= carry_out_4;
-- sum_16_temp(7 downto 4) <= sum_4;
next_state <= s3;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s3 =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(11 downto 8) <= sum_4;
next_state <= s4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when others =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(15 downto 12) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '1';
next_state <= s4;
end case;
else
a_4 <= x"0";
b_4 <= x"0";
carry_in_4 <= '0';
-- sum_16_temp <= x"0000";
carry_out_temp <= '0';
done_temp <= '0';
next_state <= s0;
end if;
end process;
end architecture structural;
还应包含任何和所有输入。这通常不会产生合成伪影，但会影响模拟结果（输出延迟，直到敏感度列表中的事件和信号出现，缺少“小故障”）
大多数合成软件忽略敏感度列表，而您正在演示问题中的映射结果
将信号分配右侧表达式中的信号添加到灵敏度列表：
state_machine:
process (state, reset_16, a_16, b_16, carry_in_16, carry_in_4)
architecture structural of sixteen_bit_adder is
-- signal sum_16_temp: std_logic_vector (15 downto 0) := x"0000";
signal carry_out_temp: std_logic;
type state_type is (s0,s1,s2,s3,s4);
signal next_state, state: state_type;
signal a_4, b_4, sum_4: std_logic_vector (3 downto 0) := x"0";
signal carry_in_4,
carry_out_4,
done_temp: std_logic := '0';
component four_bit_adder is
port (
a: in std_logic_vector (3 downto 0);
b: in std_logic_vector (3 downto 0);
carry_in: in std_logic;
sum_4: out std_logic_vector (3 downto 0);
carry_out: out std_logic
);
end component four_bit_adder;
begin
four_bit_adder1:
four_bit_adder
port map (a_4, b_4, carry_in_4, sum_4, carry_out_4);
flopping_process:
process (reset_16, clk)
begin
if reset_16 = '1' then
sum_16 <= x"0000";
carry_out_16 <= '0';
state <= s0;
done_addition <= '0';
elsif rising_edge(clk) then
case state is
when s0 =>
sum_16(3 downto 0) <= sum_4;
when s1 =>
sum_16(7 downto 4) <= sum_4;
when s2 =>
sum_16(11 downto 8) <= sum_4;
when s3 =>
sum_16(15 downto 12) <= sum_4;
when others =>
end case;
-- sum_16 <= sum_16_temp;
carry_out_16 <= carry_out_temp;
state <= next_state;
done_addition <= done_temp;
end if;
end process;
state_machine:
process (state,reset_16, a_16, b_16, carry_in_16)
begin
if reset_16 = '0' then
case state is
when s0 =>
a_4 <= a_16(3 downto 0);
b_4 <= b_16(3 downto 0);
carry_in_4 <= carry_in_16;
next_state <= s1;
-- sum_16_temp(3 downto 0) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s1 =>
a_4 <= a_16(7 downto 4);
b_4 <= b_16(7 downto 4);
carry_in_4 <= carry_out_4;
-- sum_16_temp(3 downto 0) <= sum_4;
next_state <= s2;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s2 =>
a_4 <= a_16(11 downto 8);
b_4 <= b_16(11 downto 8);
carry_in_4 <= carry_out_4;
-- sum_16_temp(7 downto 4) <= sum_4;
next_state <= s3;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s3 =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(11 downto 8) <= sum_4;
next_state <= s4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when others =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(15 downto 12) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '1';
next_state <= s4;
end case;
else
a_4 <= x"0";
b_4 <= x"0";
carry_in_4 <= '0';
-- sum_16_temp <= x"0000";
carry_out_temp <= '0';
done_temp <= '0';
next_state <= s0;
end if;
end process;
end architecture structural;
揭示了一个设计问题。在状态s1、s2、s3和s4中，您有：
carry_in_4 <= carry_out_4;
carry\u in\u 4我不愿意在没有答案的情况下给出问题的答案。没有办法知道是否还有其他问题
library ieee;
use ieee.std_logic_1164.all;
entity sixteen_bit_adder is
port (
a_16: in std_logic_vector (15 downto 0);
b_16: in std_logic_vector (15 downto 0);
carry_in_16: in std_logic;
clk: in std_logic;
reset_16: in std_logic;
done_addition: out std_logic;
sum_16: out std_logic_vector (15 downto 0);
carry_out_16: out std_logic
);
end entity sixteen_bit_adder;
architecture structural of sixteen_bit_adder is
-- signal sum_16_temp: std_logic_vector (15 downto 0) := x"0000";
signal carry_out_temp: std_logic;
type state_type is (s0,s1,s2,s3,s4);
signal next_state, state: state_type;
signal a_4, b_4, sum_4: std_logic_vector (3 downto 0) := x"0";
signal carry_in_4,
carry_out_4,
done_temp: std_logic := '0';
component four_bit_adder is
port (
a: in std_logic_vector (3 downto 0);
b: in std_logic_vector (3 downto 0);
carry_in: in std_logic;
sum_4: out std_logic_vector (3 downto 0);
carry_out: out std_logic
);
end component four_bit_adder;
begin
four_bit_adder1:
four_bit_adder
port map (a_4, b_4, carry_in_4, sum_4, carry_out_4);
flopping_process:
process (reset_16, clk)
begin
if reset_16 = '1' then
sum_16 <= x"0000";
carry_out_16 <= '0';
state <= s0;
done_addition <= '0';
elsif rising_edge(clk) then
case state is
when s0 =>
sum_16(3 downto 0) <= sum_4;
when s1 =>
sum_16(7 downto 4) <= sum_4;
when s2 =>
sum_16(11 downto 8) <= sum_4;
when s3 =>
sum_16(15 downto 12) <= sum_4;
when others =>
end case;
-- sum_16 <= sum_16_temp;
carry_out_16 <= carry_out_temp;
state <= next_state;
done_addition <= done_temp;
end if;
end process;
state_machine:
process (state, reset_16, a_16, b_16, carry_in_16, carry_in_4)
begin
if reset_16 = '0' then
case state is
when s0 =>
a_4 <= a_16(3 downto 0);
b_4 <= b_16(3 downto 0);
carry_in_4 <= carry_in_16;
next_state <= s1;
-- sum_16_temp(3 downto 0) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s1 =>
a_4 <= a_16(7 downto 4);
b_4 <= b_16(7 downto 4);
carry_in_4 <= carry_out_4;
-- sum_16_temp(3 downto 0) <= sum_4;
next_state <= s2;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s2 =>
a_4 <= a_16(11 downto 8);
b_4 <= b_16(11 downto 8);
carry_in_4 <= carry_out_4;
-- sum_16_temp(7 downto 4) <= sum_4;
next_state <= s3;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s3 =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(11 downto 8) <= sum_4;
next_state <= s4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when others =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(15 downto 12) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '1';
next_state <= s4;
end case;
else
a_4 <= x"0";
b_4 <= x"0";
carry_in_4 <= '0';
-- sum_16_temp <= x"0000";
carry_out_temp <= '0';
done_temp <= '0';
next_state <= s0;
end if;
end process;
end architecture structural;
还应包含任何和所有输入。这通常不会产生合成伪影，但会影响模拟结果（输出延迟，直到敏感度列表中的事件和信号出现，缺少“小故障”）
大多数合成软件忽略敏感度列表，而您正在演示问题中的映射结果
将信号分配右侧表达式中的信号添加到灵敏度列表：
state_machine:
process (state, reset_16, a_16, b_16, carry_in_16, carry_in_4)
architecture structural of sixteen_bit_adder is
-- signal sum_16_temp: std_logic_vector (15 downto 0) := x"0000";
signal carry_out_temp: std_logic;
type state_type is (s0,s1,s2,s3,s4);
signal next_state, state: state_type;
signal a_4, b_4, sum_4: std_logic_vector (3 downto 0) := x"0";
signal carry_in_4,
carry_out_4,
done_temp: std_logic := '0';
component four_bit_adder is
port (
a: in std_logic_vector (3 downto 0);
b: in std_logic_vector (3 downto 0);
carry_in: in std_logic;
sum_4: out std_logic_vector (3 downto 0);
carry_out: out std_logic
);
end component four_bit_adder;
begin
four_bit_adder1:
four_bit_adder
port map (a_4, b_4, carry_in_4, sum_4, carry_out_4);
flopping_process:
process (reset_16, clk)
begin
if reset_16 = '1' then
sum_16 <= x"0000";
carry_out_16 <= '0';
state <= s0;
done_addition <= '0';
elsif rising_edge(clk) then
case state is
when s0 =>
sum_16(3 downto 0) <= sum_4;
when s1 =>
sum_16(7 downto 4) <= sum_4;
when s2 =>
sum_16(11 downto 8) <= sum_4;
when s3 =>
sum_16(15 downto 12) <= sum_4;
when others =>
end case;
-- sum_16 <= sum_16_temp;
carry_out_16 <= carry_out_temp;
state <= next_state;
done_addition <= done_temp;
end if;
end process;
state_machine:
process (state,reset_16, a_16, b_16, carry_in_16)
begin
if reset_16 = '0' then
case state is
when s0 =>
a_4 <= a_16(3 downto 0);
b_4 <= b_16(3 downto 0);
carry_in_4 <= carry_in_16;
next_state <= s1;
-- sum_16_temp(3 downto 0) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s1 =>
a_4 <= a_16(7 downto 4);
b_4 <= b_16(7 downto 4);
carry_in_4 <= carry_out_4;
-- sum_16_temp(3 downto 0) <= sum_4;
next_state <= s2;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s2 =>
a_4 <= a_16(11 downto 8);
b_4 <= b_16(11 downto 8);
carry_in_4 <= carry_out_4;
-- sum_16_temp(7 downto 4) <= sum_4;
next_state <= s3;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s3 =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(11 downto 8) <= sum_4;
next_state <= s4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when others =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
-- sum_16_temp(15 downto 12) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '1';
next_state <= s4;
end case;
else
a_4 <= x"0";
b_4 <= x"0";
carry_in_4 <= '0';
-- sum_16_temp <= x"0000";
carry_out_temp <= '0';
done_temp <= '0';
next_state <= s0;
end if;
end process;
end architecture structural;
揭示了一个设计问题。在状态s1、s2、s3和s4中，您有：
carry_in_4 <= carry_out_4;
carry_在_4中有两个进程，一个包含顺序逻辑（触发器），另一个包含组合逻辑。锁存是由组合过程（标记为state_machine）中if语句的else引起的。它提供16位，而case语句一次只分配4位。在flopping_过程的elsif中，使用状态作为nybble启用sum16的片分配，nybble加法器的4位输出的所有输入（sum4而不是可以删除的sum16_temp）。前面的RTL_ROM是一种为要消除的锁存器启用门解码的状态。如果您的问题是a，我会向您展示代码中的更正并演示它们的工作原理，但没有提供应用刺激的方法。这是一个很好的例子，先画一个方框图，然后用RTL编码匹配。你有两个过程，一个包含顺序逻辑（触发器），另一个包含组合逻辑。锁存是由组合过程（标记为state_machine）中if语句的else引起的。它提供16位，而case语句一次只分配4位。在flopping_过程的elsif中，使用状态作为nybble启用sum16的片分配，nybble加法器的4位输出的所有输入（sum4而不是可以删除的sum16_temp）。前面的RTL_ROM是一种为要消除的锁存器启用门解码的状态。如果您的问题是a，我会向您展示代码中的更正并演示它们的工作原理，但没有提供应用刺激的方法。这似乎是一个很好的例子，通过先画一个方框图，然后进行RTL编码来匹配。