为什么赢了';t VHDL“;inout“;当用作输出时,应为信号分配一个值
我有一个桥的VHDL描述,双向信号“mem_data_port0”没有被赋值,不管我写了什么。FPGA上的引脚被相应地分配,但没有输出 我有下面的代码(适用于进入较大系统的FPGA,因此注释将反映非FPGA的其他系统组件) 仅供参考:FPGA为Lattice LCMXO2-7000HC 关于分配“mem_data_port0”有什么提示吗为什么赢了';t VHDL“;inout“;当用作输出时,应为信号分配一个值,vhdl,fpga,Vhdl,Fpga,我有一个桥的VHDL描述,双向信号“mem_data_port0”没有被赋值,不管我写了什么。FPGA上的引脚被相应地分配,但没有输出 我有下面的代码(适用于进入较大系统的FPGA,因此注释将反映非FPGA的其他系统组件) 仅供参考:FPGA为Lattice LCMXO2-7000HC 关于分配“mem_data_port0”有什么提示吗 ieee库; 使用ieee.std_logic_1164.all; 使用ieee.std_logic_arith.all; 使用ieee.std_logic_
ieee库;
使用ieee.std_logic_1164.all;
使用ieee.std_logic_arith.all;
使用ieee.std_logic_unsigned.all;
--使用ieee.std\u logic\u signed.all;
使用ieee.std_logic_arith.all;
使用ieee.numeric_std.all;
machxo2图书馆;
使用machxo2.all;
实体SinglePhasePowerAnalyzerBridge为
港口(
output0:out std_logic;--虚拟、未分配的输出
输出1:输出标准逻辑;
输出2:输出标准逻辑;
输出3:输出标准逻辑;
输出4:输出标准_逻辑;
输出5:输出标准逻辑;
输出6:输出标准逻辑;
输出7:输出标准逻辑;
accq_数据输入:标准逻辑向量(15向下至0);--采集数据输入
accq\U clk:标准逻辑中;--采集时钟输入
accq_数据准备就绪:在标准逻辑中;--数据准备就绪,0:发送电压/电流数据,1:发送频率数据
accq\U复位:在标准逻辑中;--ACCQUISION复位(低电平有效)
accq\u电压\电流:在标准逻辑中;--电压和电流的accq选择0:电压,1:电流
缓冲区数据端口0:输出标准逻辑向量(15向下到0);--缓冲区数据
缓冲区地址端口0:标准逻辑向量(12向下到0);--缓冲区地址低位
缓冲区地址高端口0:标准逻辑向量(2到0);--缓冲区地址高位
缓冲区\高字节\端口0:在标准\逻辑中;--高字节启用
缓冲区\低字节\端口0:在标准\逻辑中;--低字节启用
缓冲区写入端口0:在标准逻辑中;--写入启用
缓冲区输出端口0:在标准逻辑中;--输出启用
缓冲区内存端口0:在标准逻辑中;--内存启用
缓冲区中断输出:输出标准逻辑;
--引脚连接到外部SRAM存储器
内存数据端口0:inout标准逻辑向量(15到0);
内存地址端口0:输出标准逻辑向量(12到0);
mem_地址_high_端口0:输出标准逻辑_向量(3向下至0);
mem_memory_en_port0:输出标准逻辑:='1';
内存输出端口0:out标准逻辑:='1';
mem_write_en_port0:out标准逻辑:='1';
mem_high_byte_en_port0:输出标准逻辑:='0';
mem_low_byte_en_port0:out标准逻辑:='0';
调试输出:输出标准逻辑——调试输出
);
端部单相功率分析仪电桥;
介绍了单相电力分析仪桥的rtl体系结构
信号频率存储缓冲区:标准逻辑向量(15到0);--频率缓冲器
信号电压\存储\指针:整数范围0至8191;
信号电流\存储\指针:整数范围0至8191;
信号-信号-数据-输入:标准-逻辑-向量(15到0);
信号灯:标准逻辑;
信号反向accq clk:标准逻辑;
信号accq数据就绪:标准逻辑;
信号accq复位:标准逻辑;
信号电压电流:标准逻辑;
信号延迟逆时钟:标准逻辑;
信号缓冲区数据端口0:标准逻辑向量(15到0);
信号缓冲区地址端口0:标准逻辑向量(12到0);
信号缓冲区地址高位端口0:std逻辑向量(2向下至0);
信号缓冲区高位字节端口0:std逻辑;
信号缓冲区低字节端口0:标准逻辑;
信号缓冲写入端口0:标准逻辑;
信号缓冲输出端口0:标准逻辑;
信号缓冲存储器端口0:标准逻辑;
开始
我已经在Modelsim上试用了你的代码。虽然我不能评论mem_data_port0行为的正确性,但它确实会根据其他相关信号获得赋值,因此对于输出方向,它是有效的
如果你说的是,你不能从外部给它赋值,我能想到的就是,你忘了在输入模式下给它赋值,但是你给了,所以那就完了
一种解释可能是,您的实体不是顶级实体,这将导致inout端口不可用(inout在FPGA内部没有意义,只是在设计的顶级)。我建议您将代码简化为一个较小的示例。通过给它分配一个值以将其用作输出,将“ZZZZZZZ…”分配给它并将其当作输入来读取,请参见David Clan:将accq_重置为高,accq_data_ready为低,将accq_data_中任何值的数据放入,并将accq_时钟计时。在accq_时钟的上升沿上,mem_data_port0的值应与accq_data_in的值相同。注意:名称的第一部分为“mem_”的每个端口信号都会发送到具有异步并行接口的外部SRAM,具有“buffer_”的端口信号用作MCU的类似内存的接口。中的采集数据以递增地址存储在内存中。当采集时钟上升沿出现时,会发生的情况是“mem_data_port0”应该被分配采集数据in,并且在accq时钟高之后,内存的写入启用引脚会稍微变低。我通过延迟线将accq_时钟输出的倒数发送到内存的WE引脚。连接到“mem_”信号的内存是ISSI IS62WV12816BLL,信号名称与内存芯片的引脚相同。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.all;
entity SinglePhasePowerAnalyzerBridge is
port(
output0 : out std_logic; -- dummy, unassigned outputs
output1 : out std_logic;
output2 : out std_logic;
output3 : out std_logic;
output4 : out std_logic;
output5 : out std_logic;
output6 : out std_logic;
output7 : out std_logic;
accq_data_in : in std_logic_vector (15 downto 0); -- accquisition data in
accq_clk : in std_logic; -- accquisition clock in
accq_data_ready : in std_logic; -- data ready in 0: sending voltage/current data, 1: sending frequency data
accq_reset : in std_logic; -- accquisition reset (active low)
accq_voltage_current : in std_logic; -- accquisition select for voltage and current 0: voltage, 1: current
buffer_data_port0 : out std_logic_vector (15 downto 0); -- buffer data
buffer_address_port0 : in std_logic_vector(12 downto 0); -- buffer address low bits
buffer_address_high_port0 : in std_logic_vector(2 downto 0); -- buffer address high bits
buffer_high_byte_en_port0 : in std_logic; -- high byte enable
buffer_low_byte_en_port0 : in std_logic; -- low byte enable
buffer_write_en_port0 : in std_logic; -- write enable
buffer_output_en_port0 : in std_logic; -- output enable
buffer_memory_en_port0 : in std_logic; -- memory enable
buffer_interrupt_out : out std_logic;
-- pins going to external SRAM memory
mem_data_port0 : inout std_logic_vector (15 downto 0);
mem_address_port0 : out std_logic_vector(12 downto 0);
mem_address_high_port0 : out std_logic_vector (3 downto 0);
mem_memory_en_port0 : out std_logic := '1';
mem_output_en_port0 : out std_logic := '1';
mem_write_en_port0 : out std_logic := '1';
mem_high_byte_en_port0 : out std_logic := '0';
mem_low_byte_en_port0 : out std_logic := '0';
debug_out : out std_logic -- debug output
);
end SinglePhasePowerAnalyzerBridge;
architecture rtl of SinglePhasePowerAnalyzerBridge is
signal frequency_storage_buffer : std_logic_vector (15 downto 0); -- frequency buffer
signal voltage_storage_pointer : integer range 0 to 8191;
signal current_storage_pointer : integer range 0 to 8191;
signal signal_accq_data_in : std_logic_vector (15 downto 0);
signal signal_accq_clk : std_logic;
signal signal_inverse_accq_clk : std_logic;
signal signal_accq_data_ready : std_logic;
signal signal_accq_reset : std_logic;
signal signal_accq_voltage_current : std_logic;
signal signal_delayed_inverse_accq_clk : std_logic;
signal signal_buffer_data_port0 : std_logic_vector (15 downto 0);
signal signal_buffer_address_port0 : std_logic_vector(12 downto 0);
signal signal_buffer_address_high_port0 : std_logic_vector(2 downto 0);
signal signal_buffer_high_byte_en_port0 : std_logic;
signal signal_buffer_low_byte_en_port0 : std_logic;
signal signal_buffer_write_en_port0 : std_logic;
signal signal_buffer_output_en_port0 : std_logic;
signal signal_buffer_memory_en_port0 : std_logic;
begin
signal_accq_data_in <= accq_data_in; -- connect all the pins to internal signals
signal_accq_clk <= accq_clk;
signal_accq_data_ready <= accq_data_ready;
signal_accq_reset <= accq_reset;
signal_accq_voltage_current <= accq_voltage_current;
signal_inverse_accq_clk <= not signal_accq_clk;
--debug_out <= signal_delayed_inverse_accq_clk;
signal_buffer_address_port0 <= buffer_address_port0;
signal_buffer_address_high_port0 <= buffer_address_high_port0;
signal_buffer_high_byte_en_port0 <= buffer_high_byte_en_port0;
signal_buffer_low_byte_en_port0 <= buffer_low_byte_en_port0;
signal_buffer_write_en_port0 <= buffer_write_en_port0;
signal_buffer_output_en_port0 <= buffer_output_en_port0;
signal_buffer_memory_en_port0 <= buffer_memory_en_port0;
buffer_interrupt_out <= not signal_accq_data_ready;
output2 <= signal_accq_data_ready; -- dummy outputs, so the input pins are not left uncommected
output3 <= signal_accq_clk;
output4 <= signal_accq_reset;
output5 <= signal_accq_voltage_current;
general_event : process(signal_accq_clk, signal_accq_data_ready, signal_accq_data_in, signal_accq_voltage_current, signal_accq_reset,
signal_buffer_memory_en_port0, signal_buffer_output_en_port0, signal_buffer_write_en_port0, signal_buffer_address_high_port0, signal_buffer_address_port0,
signal_buffer_data_port0, frequency_storage_buffer, signal_accq_reset, signal_accq_data_ready, voltage_storage_pointer, current_storage_pointer)
begin
if(signal_accq_data_ready = '0') then -- when data from the acquisition controller comes in
mem_output_en_port0 <= '1'; -- disable memory output
mem_memory_en_port0 <= '0'; -- enable memory
mem_write_en_port0 <= signal_inverse_accq_clk; -- send the acquisition clock to the memory write enable pin
if(signal_accq_reset = '1') then -- if reset is not activated...
accq_clk_edge : if(rising_edge(signal_accq_clk)) then -- process on clock rising edge
if(signal_accq_voltage_current = '1') then -- if sending current data
mem_data_port0 <= signal_accq_data_in; -- store the data in the current buffer
mem_address_port0 <= std_logic_vector(to_unsigned(current_storage_pointer, 13));
mem_address_high_port0 <= "0001"; -- sending current data to memory
current_storage_pointer <= (current_storage_pointer + 1); -- increment the counter
elsif (signal_accq_voltage_current = '0') then -- do the same if sending voltage data
--mem_data_port0 <= signal_accq_data_in; -- store the data in the voltage buffer
mem_data_port0 <= "1111111111111111";
mem_address_port0 <= std_logic_vector(to_unsigned(voltage_storage_pointer, 13));
mem_address_high_port0 <= "0000"; -- sending voltage data to memory
voltage_storage_pointer <= (voltage_storage_pointer + 1); -- increment the counter
end if;
end if accq_clk_edge;
else -- if reset is activated...
voltage_storage_pointer <= 0; -- reset everything to 0
current_storage_pointer <= 0; -- reset everything to 0
end if;
--end process accq_event;
elsif (signal_accq_data_ready = '1') then -- if data ready is high, the buffer is in read mode
mem_data_port0 <= "ZZZZZZZZZZZZZZZZ"; -- set memory data lines to input, or read mode
mem_write_en_port0 <= '1'; -- disable writing to the memory
mem_output_en_port0 <= '0'; -- enable memory output
mem_address_port0 <= signal_buffer_address_port0; -- select the appropriate addreess
mem_address_high_port0 (2 downto 0) <= signal_buffer_address_high_port0; -- do the same with the high bits
if(rising_edge(signal_accq_clk) and signal_accq_reset = '1') then -- if the accquisition MCU is writing with the data ready pin high
frequency_storage_buffer <= signal_accq_data_in; -- store the frequency value that it's sending
end if;
if(signal_accq_reset = '0') then -- reset as before if reset is enabled
voltage_storage_pointer <= 0; -- reset everything to 0
current_storage_pointer <= 0; -- reset everything to 0
end if;
if(signal_buffer_memory_en_port0 = '0' and signal_buffer_write_en_port0 = '1' and signal_accq_data_ready = '1' and signal_accq_reset = '1') then -- memory enabled and write enable high...
case signal_buffer_address_high_port0 is
when "000" => signal_buffer_data_port0 <= mem_data_port0; -- output data to downstream MCUs as needed
when "001" => signal_buffer_data_port0 <= mem_data_port0;
when "010" => signal_buffer_data_port0 <= frequency_storage_buffer;
when "011" => signal_buffer_data_port0 <= std_logic_vector(to_unsigned(voltage_storage_pointer, 16));
when "100" => signal_buffer_data_port0 <= std_logic_vector(to_unsigned(current_storage_pointer, 16));
when "111" => signal_buffer_data_port0 <= "1010000001010110"; -- 0xA056
when others=>
end case;
end if;
if(signal_buffer_output_en_port0 = '0') then
--buffer_data_port0(7 downto 0) <= signal_buffer_data_port0 (15 downto 8);
--buffer_data_port0(15 downto 8) <= signal_buffer_data_port0 (7 downto 0);
buffer_data_port0 <= signal_buffer_data_port0;
else
buffer_data_port0 <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
end process general_event;
output6 <= signal_buffer_high_byte_en_port0;
output7 <= signal_buffer_low_byte_en_port0;
end rtl;