VHDL测试台代码未显示1位全加器的输出结果

这里的代码有一些警告，但没有发现错误，但测试台上的这个全加器输出波形和进位并没有显示。进位和进位输出中显示了u，但不是输入很好，只有进位和进位输出是问题的原因，在这里有一些警告，有时我对警告有疑问，这里我附上了图片，请参考，并给我一些解决此问题的建议

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错误是因为它找不到

全加器的代码。您需要在模拟之前添加它。这不是一个错误，这是一个警告，如果这是一个错误，那么我不能像上面所附的图片那样运行模拟。在一个或多个组件实例化未绑定的情况下详细阐述设计层次结构并不违法，可以将其视为未安装组件的面包板。这是VHDL标准特别允许的。您没有显式绑定，默认绑定不会将实体完整加法器标识为直接可见，它没有被成功分析（编译）并添加到工作库中，也没有使它在另一个参考库中可见的库子句和use子句。模拟器供应商为那些不想让组件处于未绑定状态的人添加了警告。这
——对于U1：全加器使用实体工作。全加器（MY_数据流）未注释且UUT代替U1将是提供显式绑定指示的配置规范。您的课程讲师希望您能够成功地分析实体全加器和体系结构数据流，并将其放入当前的工作库中。如果有明确的绑定指示，则会出现错误。IEEE Std 1076-2008 13.5分析顺序“如果在尝试分析设计单元时检测到任何错误，则尝试的分析将被拒绝，并且对当前工作库没有任何影响。”您是否尝试将全加器及其体系结构分析到当前的工作库中，但失败了？
 -- 1-bit full adder testbench
 -- A testbench is used to rigorously tests a design that you have made.
 -- The output of the testbench should allow the designer to see if
 -- the design worked. The testbench should also report where the testbench
 -- failed.
  LIBRARY IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  -- Declare a testbench. Notice that the testbench does not have any input
 -- or output ports.
entity tb_1bitfulladder is
end tb_1bitfulladder;
 -- Describes the functionality of the tesbench.
 architecture MY_TEST of tb_1bitfulladder is
 -- The object that we wish to test is declared as a component of
 -- the test bench. Its functionality has already been described elsewhere.
 -- This simply describes what the object's inputs and outputs are, it
 -- does not actually create the object.
     component FULL_ADDER
      port( x, y, Cin : in STD_LOGIC;
       s, Cout : out STD_LOGIC );
     end component;
     -- Specifies which description of the adder you will use.
     --for U1: FULL_ADDER use entity WORK.FULL_ADDER(MY_DATAFLOW);
     -- Create a set of signals which will be associated with both the inputs
     -- and outputs of the component that we wish to test.
    signal X_s, Y_s : STD_LOGIC:='0';
    signal CIN_s : STD_LOGIC:='0';
    signal SUM_s : STD_LOGIC;
    signal COUT_s : STD_LOGIC;
    -- This is where the testbench for the FULL_ADDER actually begins.
  BEGIN
   -- Create a 1-bit full adder in the testbench.
    -- The signals specified above are mapped to their appropriate
     -- roles in the 1-bit full adder which we have created.
  UUT: FULL_ADDER port map (x=>X_s,       --(//this line has some warning i put it below END Othecode)
                         y=>Y_s,
                         Cin=>CIN_s,
                         s => SUM_s, 
                         Cout=> COUT_s
);
  -- The process is where the actual testing is done.       
  -- stimulus process
   stim_proc:process
      begin
  -- We are now going to set the inputs of the adder and test
  -- the outputs to verify the functionality of our 1-bit full adder.
  -- Case 0 : 0+0 with carry in of 0.
  -- Set the signals for the inputs.
   X_s <= '0';
   Y_s <= '0';
   CIN_s <= '0';
 -- Wait a short amount of time and then check to see if the
 -- outputs are what they should be. If not, then report an error
  -- so that we will know there is a problem.
  wait for 10 ns;

  assert ( SUM_s = '0' ) report "Failed Case 0 - SUM" severity error;
  assert ( COUT_s = '0' ) report "Failed Case 0 - COUT" severity error;
  wait for 40 ns;
   -- Carry out the same process outlined above for the other 7 cases.
   -- Case 1 : 0+0 with carry in of 1.
   X_s <= '0';
   Y_s <= '0';
   CIN_s <= '1';
   wait for 10 ns;
   assert ( SUM_s = '1' ) report "Failed Case 1 - SUM" severity error;
   assert ( COUT_s = '0' ) report "Failed Case 1 - COUT" severity error;
   wait for 40 ns;
-- Case 2 : 0+1 with carry in of 0.
   X_s <= '0';
   Y_s <= '1';
   CIN_s <= '0';
   wait for 10 ns;
   assert ( SUM_s = '1' ) report "Failed Case 2 - SUM" severity error;
   assert ( COUT_s = '0' ) report "Failed Case 2 - COUT" severity error;
   wait for 40 ns;
  -- Case 3 : 0+1 with carry in of 1.
   X_s <= '0';
   Y_s <= '1';
  CIN_s <= '1';
  wait for 10 ns;
  assert ( SUM_s = '0' ) report "Failed Case 3 - SUM" severity error;
  assert ( COUT_s = '1' ) report "Failed Case 3 - COUT" severity error;
  wait for 40 ns;
 -- Case 4 : 1+0 with carry in of 0.
  X_s <= '1';
  Y_s <= '0';
 CIN_s <= '0';
 wait for 10 ns;
 assert ( SUM_s = '1' ) report "Failed Case 4 - SUM" severity error;
 assert ( COUT_s = '0' ) report "Failed Case 4 - COUT" severity error;
 wait for 40 ns;
 -- Case 5 : 1+0 with carry in of 1.
  X_s <= '1';
  Y_s <= '0';
  CIN_s <= '1';
  wait for 10 ns;
  assert ( SUM_s = '0' ) report "Failed Case 5 - SUM" severity error;
  assert ( COUT_s = '1' ) report "Failed Case 5 - COUT" severity error;
  wait for 40 ns;
  -- Case 6 : 1+1 with carry in of 0.
   X_s <= '1';
   Y_s <= '1';
   CIN_s <= '0';
   wait for 10 ns;
    assert ( SUM_s = '0' ) report "Failed Case 6 - SUM" severity error;
    assert ( COUT_s = '1' ) report "Failed Case 6 - COUT" severity error;
   wait for 40 ns;
  -- Case 7 : 1+1 with carry in of 1.
   X_s <= '1';
   Y_s <= '1';
   CIN_s <= '1';

   wait for 10 ns;
  assert ( SUM_s = '1' ) report "Failed Case 7 - SUM" severity error;
  assert ( COUT_s = '1' ) report "Failed Case 7 - COUT" severity error;
  wait for 40 ns;
  end process;
END MY_TEST;