VHDL：使用无符号大小写选择器

我想使用STD_LOGIC_向量输入，该输入应转换为无符号，作为Case语句中的选择器，如下所示：

`  port ( clk_24 : in std_logic;
         frequency : in STD_LOGIC_VECTOR(2 downto 0);
         led : out std_logic);
case unsigned(frequency) is
  when to_unsigned(1, 3) => counterlimit <= to_unsigned(48000000, 32);
  when to_unsigned(2, 3) => counterlimit <= to_unsigned(24000000, 32);
  when to_unsigned(3, 3) => counterlimit <= to_unsigned(12000000, 32);
  when to_unsigned(4, 3) => counterlimit <= to_unsigned(6000000, 32);
  when to_unsigned(5, 3) => counterlimit <= to_unsigned(3000000, 32);
  when to_unsigned(6, 3) => counterlimit <= to_unsigned(1500000, 32);
  when to_unsigned(7, 3) => counterlimit <= to_unsigned(750000, 32);            
end case;

`端口（时钟24：标准逻辑中；
频率：标准逻辑向量（2到0）；
led：输出标准（U逻辑）；
大小写无符号（频率）为
什么时候去_unsigned（1，3）=>counterlimit counterlimit counterlimit counterlimit counterlimit counterlimit不确定它为什么认为它是一个无约束数组，但您可以（应该？）执行以下操作：

case to_integer(unsigned(frequency)) is
  when 1 =>
    ...

更容易阅读，并且应该编译得很好。
不确定它认为它是无约束数组的确切原因，但是您可以（应该？）执行以下操作：

case to_integer(unsigned(frequency)) is
  when 1 =>
    ...

更容易阅读，并且应该编译得很好。
除了fru1bat的建议之外，您还需要一个覆盖0和8到整数最大值的其他选项，或者一个覆盖选项0的中间变量，并带有范围约束：

其他选择0到整数的最大值：

UNLABELED:
    process(frequency)
    begin
        case to_integer(unsigned(frequency)) is
            when 1 => counterlimit <= to_unsigned(48000000, 32);
            when 2 => counterlimit <= to_unsigned(24000000, 32);
            when 3 => counterlimit <= to_unsigned(12000000, 32);
            when 4 => counterlimit <= to_unsigned(6000000, 32);
            when 5 => counterlimit <= to_unsigned(3000000, 32);
            when 6 => counterlimit <= to_unsigned(1500000, 32);
            when 7 => counterlimit <= to_unsigned(750000, 32);
         -- when 0 to integer'MAX;
            when others => counterlimit <= to_unsigned(96000000, 32);
        end case;
    end process;

未标记：
过程（频率）
开始
大小写到_整数（无符号（频率））为
当1=>counterlimit counterlimit counterlimit counterlimit counterlimit counterlimit counterlimit counterlimit除fru1bat的建议外，您还需要一个覆盖0和8到integer'MAX的其他选项，或者一个覆盖选项0且带有范围约束的中间变量：

其他选择0到整数的最大值：

UNLABELED:
    process(frequency)
    begin
        case to_integer(unsigned(frequency)) is
            when 1 => counterlimit <= to_unsigned(48000000, 32);
            when 2 => counterlimit <= to_unsigned(24000000, 32);
            when 3 => counterlimit <= to_unsigned(12000000, 32);
            when 4 => counterlimit <= to_unsigned(6000000, 32);
            when 5 => counterlimit <= to_unsigned(3000000, 32);
            when 6 => counterlimit <= to_unsigned(1500000, 32);
            when 7 => counterlimit <= to_unsigned(750000, 32);
         -- when 0 to integer'MAX;
            when others => counterlimit <= to_unsigned(96000000, 32);
        end case;
    end process;

未标记：
过程（频率）
开始
大小写到_整数（无符号（频率））为
当1=>counterlimit counterlimit counterlimit counterlimit counterlimit当您添加案例others或0时：
when others=>counterlimit当您添加案例others或0时：
when others=>counterlimit