If statement 如果Else参数化,则生成块编译时
我希望能够使用generate块参数化一些行为级别的Verilog。该模块是一个可重新配置的读出和FIFO块,主要是为了使我们可以编码这一个,只需在顶层使用一个参数 假设我们有:If statement 如果Else参数化,则生成块编译时,if-statement,verilog,If Statement,Verilog,我希望能够使用generate块参数化一些行为级别的Verilog。该模块是一个可重新配置的读出和FIFO块,主要是为了使我们可以编码这一个,只需在顶层使用一个参数 假设我们有: always @(posedge write_out_clk or posedge RESETN) begin if (RESETN) SENSE_ADDR <= 0; else if (enb[0] == 1) SENSE_ADDR <= 1;
always @(posedge write_out_clk or posedge RESETN)
begin
if (RESETN)
SENSE_ADDR <= 0;
else if (enb[0] == 1)
SENSE_ADDR <= 1; // for example but may be some other wire/bus etc
else if (enb[1] == 2)
SENSE_ADDR <= 1; // for example but may be some other wire/bus etc
else
SENSE_ADDR <= SENSE_ADDR;
end
end
always@(posedge写出来或posedge重置)
开始
如果(重置)
这能满足你的需要吗?不需要生成
module mux #(
parameter WIDTH = 5,
parameter NUM = 2,
parameter NUMLG = $clog2(NUM)
) (
input [NUMLG -1:0] sel,
input [WIDTH - 1:0] in [0:NUM-1],
output [WIDTH - 1:0] out
);
assign out = in[sel];
endmodule
如果你的模拟器不支持SystemVerilog那么好,你就必须修改它来吹出输入数组,但概念是一样的。你不需要生成块。添加一个组合always块来计算下一个\u SENSE\u ADDR
,该块将跳转到SENSE\u ADDR
always @(posedge write_out_clk or posedge RESETN)
begin
if (RESETN)
SENSE_ADDR <= 0;
else
SENSE_ADDR <= next_SENSE_ADDR;
end
integer idx;
always @* begin // @(SENSE_ADDR or enb or some_wire)
next_SENSE_ADDR = SENSE_ADDR; // default, value if enb is all 0
// count down because lsb has higher priority
for ( idx=FIFO_SUB_BLOCKS-1; idx>=0; idx-- ) begin
if ( enb[idx] )
next_SENSE_ADDR = some_wire[idx];
end
end
always@(posedge写出来或posedge重置)
开始
如果(重置)
感官地址
always @(posedge write_out_clk or posedge RESETN)
begin
if (RESETN)
SENSE_ADDR <= 0;
else
SENSE_ADDR <= next_SENSE_ADDR;
end
integer idx;
always @* begin // @(SENSE_ADDR or enb or some_wire)
next_SENSE_ADDR = SENSE_ADDR; // default, value if enb is all 0
// count down because lsb has higher priority
for ( idx=FIFO_SUB_BLOCKS-1; idx>=0; idx-- ) begin
if ( enb[idx] )
next_SENSE_ADDR = some_wire[idx];
end
end