Verilog-我得到了；非法输出或输入输出端口连接（端口&"x27；q&"x27；）；为我的体系结构模拟测试台时出错

这就是我试图实现的体系结构。但在测试台模拟期间，modelsim中出现了错误，但我的编译成功了

# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(8): Illegal output or inout port connection (port 'q').
#         Region: /mgu_tb/m1/a1
# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(10): Illegal output or inout port connection (port 'q').
#         Region: /mgu_tb/m1/a3
# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(12): Illegal output or inout port connection (port 'q').
#         Region: /mgu_tb/m1/a5
# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(14): Illegal output or inout port connection (port 'q').
#         Region: /mgu_tb/m1/a7

主模块：

module mgu(in,clk,rst,c0,c1,c2,c3);
//module mgu(in,clk,rst);
input in,clk,rst;
output reg c0,c1,c2,c3;
//reg c0,c1,c2,c3;
wire w1,w2,w3;

    dff a1 (.clk(clk),.rst(rst),.din(in),.q(c0));
    xor a2 (w1,c0,c1);
    dff a3 (clk,rst,w1,c1);
    xor a4 (w2,c1,c2);
    dff a5 (clk,rst,w2,c2);
    xor a6 (w3,c2,c3);
    dff a7 (clk,rst,w3,c3);

endmodule    

D触发器

module dff (clk,rst,din,q);
input clk,din,rst;
output reg q;
always @ ( posedge clk)
    begin
            if (rst)
            q<=1'b0;
           else
           q<=din;
    end
endmodule

无需在主模块输出端口中使用“

output reg

”。只需“

输出”

”即可

module mgu_tb( );
reg in,clk,rst;
wire c0,c1,c2,c3;

mgu m1(in,clk,rst,c0,c1,c2,c3);

initial
begin
    clk = 1'b0;
    rst = 1'b1;
    in = 1'b0;
end

always #5 clk = ~clk;

initial
begin
    #10 rst = 1'b0;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;

end

endmodule