为什么我的VHDL测试台给我'；U'；对于输出？使用4x1MUX和Dflipflop

我正在尝试为一个可以向右移动、向左移动、向右旋转和向左旋转的设备编写代码。正如你在这张照片中看到的。

因此，我为4x1 MUX和DFlipFlop模块编写了代码，并将它们与端口映射一起用于我的主模块。所以当我做一个测试台时，我的输出是“U”。 您可以在下面看到我的代码：

4x1多路复用器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity MUX4x1 is
Port ( in1 : in std_logic; -- mux input1
in2 : in std_logic; -- mux input2
in3 : in std_logic; -- mux input3
in4 : in std_logic; -- mux input4
sel : in std_logic_vector(1 downto 0); -- selection line
dataout : out std_logic); -- output data
end MUX4x1;

architecture Behavioral of MUX4x1 is
begin
-- This process for mux logic
process (sel, in1, in2, in3, in4)
begin
case SEL is 
when "00" => dataout <= in1; 
when "01" => dataout <= in2;
when "10" => dataout <= in3;
when "11" => dataout <= in4;
when others => dataout <= '0';
end case;
end process;

end Behavioral;

IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
实体MUX4x1为
端口（in1:in标准_逻辑；--mux输入1
in2:in标准_逻辑；--mux输入2
in3:in标准_逻辑；--mux输入3
in4:in标准_逻辑；--mux输入4
sel：标准逻辑向量（1到0）；--选择行
数据输出：输出标准（U逻辑）；--输出数据
末端MUX4x1；
MUX4x1的架构是
开始
--此过程适用于多路复用逻辑
过程（sel、in1、in2、in3、in4）
开始
case SEL是
当“00”=>dataout dataout时，您没有在DFF中重置或预设q（还要注意的是，当前没有FPGA设备同时提供预设和清除DFF）。没有显式赋值，std_逻辑类型的默认值为“U”。如果不使用
输入
@user1155120，电路的实用性有限：预设和重置/清除是同步的，因此可以实现。（但这也使得D-ff与大多数设计师称之为“标准”的D-ff不兼容）。您没有在DFF中重置或预设q（还要注意的是，当前没有FPGA设备同时提供预设和清除的DFF）。没有显式赋值，std_逻辑类型的默认值为“U”。如果不使用
输入
@user1155120，电路的实用性有限：预设和重置/清除是同步的，因此可以实现。（但这也使得D-ff与大多数设计师所称的“标准”D-ff不兼容）。
entity Dflipflop is
port
   (
  clk : in std_logic;

  rst : in std_logic;
  pre : in std_logic;
  ce  : in std_logic;

  d : in std_logic;

  q : out std_logic
   );
end Dflipflop;

architecture Behavioral of Dflipflop is

begin
   process (clk) is
   begin
      if rising_edge(clk) then  
         if (rst='1') then   
            q <= '0';
         elsif (pre='1') then
            q <= '1';
         elsif (ce='1') then
            if (d ='1') then
             q <= '1';
     elsif (d ='0') then 
         q<= '0';
        end if;
     end if;
  end if;
 end process;


end Behavioral;

entity Main is
port(
--input: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
clk: in std_logic;
output0: out std_logic;
output1: out std_logic;
output2: out std_logic;
output3: out std_logic
);
end Main;

architecture Behavioral of Main is


component MUX4x1 is
Port ( 
in1 : in std_logic; -- mux input1
in2 : in std_logic; -- mux input2
in3 : in std_logic; -- mux input3
in4 : in std_logic; -- mux input4
sel : in std_logic_vector(1 downto 0); -- selection line
dataout : out std_logic); -- output data
end component;


component Dflipflop is
port
   (
     clk : in std_logic;

     rst : in std_logic;
     pre : in std_logic;
     ce  : in std_logic;

     d : in std_logic;

      q : out std_logic
   );
end component;

signal temp: std_logic_vector(3 downto 0);
signal A:std_logic_vector(3 downto 0) := "0010";
begin
MUX1: MUX4x1 port map (A(1),'0',A(1),A(3),s,temp(0));
MUX2: MUX4x1 port map (A(2),A(0),A(3),A(1),s,temp(1));
MUX3: MUX4x1 port map (A(3),A(1),A(3),A(1),s,temp(2));
MUX4: MUX4x1 port map (A(0),A(2),A(0),A(2),s,temp(3));
FF1: Dflipflop port map(clk,'0','0','1',temp(0),A(0));
FF2: Dflipflop port map(clk,'0','0','1',temp(1),A(1));
FF3: Dflipflop port map(clk,'0','0','1',temp(2),A(2));
FF4: Dflipflop port map(clk,'0','0','1',temp(3),A(3));
output0<=A(0);
output1<=A(1);
output2<=A(2);
output3<=A(3);
end Behavioral;

ENTITY TestBench IS
END TestBench;

ARCHITECTURE behavior OF TestBench IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Main
PORT(
     s : IN  std_logic_vector(1 downto 0);
     clk : IN  std_logic;
     output0 : OUT  std_logic;
     output1 : OUT  std_logic;
     output2 : OUT  std_logic;
     output3 : OUT  std_logic
    );
END COMPONENT;


   --Inputs
   signal s : std_logic_vector(1 downto 0) := (others => '0');
   signal clk : std_logic := '0';

    --Outputs
   signal output0 : std_logic;
   signal output1 : std_logic;
   signal output2 : std_logic;
   signal output3 : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Main PORT MAP (
          s => s,
          clk => clk,
          output0 => output0,
          output1 => output1,
          output2 => output2,
          output3 => output3
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

 END;