System verilog 声明枚举类型的数组

我想做以下工作：

typedef enum {a, b, c} my_type_e;
typedef enum {receive, transmit} dir_e;

class my_class #(type my_type_e);
  my_type_e variable_name;
endclass

但我想让“variable_name”成为一个使用dir_e作为索引的数组。比如说

my_class class_h;
class_h.variable_name[rx] = a;

或

---

这有意义吗？

您想声明一个关联数组

class my_class #(type my_type_e);
  my_type_e variable_name[dir_e];
endclass

my_class class_h;
class_h.variable_name[receive] = a;

---

假设您想使用参数，我不会让类型参数与现有类型匹配。另外，一些模拟器仍然不支持没有默认值

typedef enum {a, b, c} my_type_e;
typedef enum {receive, transmit} dir_e;

class my_class #(type T=my_type_e, type K=dir_e);
  T variable_name[K];
endclass

my_class class_h;
class_h.variable_name[receive] = a;

typedef enum {a, b, c} my_type_e;
typedef enum {receive, transmit} dir_e;

class my_class #(type T=my_type_e, type K=dir_e);
  T variable_name[K];
endclass

my_class class_h;
class_h.variable_name[receive] = a;