Syntax 函数语法未编译-VHDL

Syntax 函数语法未编译-VHDL,syntax,vhdl,Syntax,Vhdl,我完全是VHDL的初学者,我不知道为什么会出错。如果我删除该函数,所有内容都会正确编译,但当我将其放回时,会出现以下错误: “函数”附近的语法错误 “开始”附近的语法错误 “when”附近的语法错误 “when”附近的语法错误 你明白了 以下是被上帝抛弃的功能: function decod ( x : in integer range 0 to 9) return STD_LOGIC_VECTOR is variable temp : in STD_LOGIC_VECTOR (6 d

我完全是VHDL的初学者,我不知道为什么会出错。如果我删除该函数,所有内容都会正确编译,但当我将其放回时,会出现以下错误:

“函数”附近的语法错误

“开始”附近的语法错误

“when”附近的语法错误

“when”附近的语法错误

你明白了

以下是被上帝抛弃的功能:

    function decod ( x : in integer range 0 to 9)
return STD_LOGIC_VECTOR is 
variable temp : in STD_LOGIC_VECTOR (6 downto 0);
    begin
    case x is
        when 0 => temp <= "0000001"; -- 0
        when 1 => temp <= "1001111"; -- 1
        when 2 => temp <= "0010010"; -- 2
        when 3 => temp <= "0000110"; -- 3 
        when 4 => temp <= "1001100"; -- 4
        when 5 => temp <= "0100100"; -- 5
        when 6 => temp <= "0100000"; -- 6
        when 7 => temp <= "0001111"; -- 7
        when 8 => temp <= "0000000"; -- 8 
        when 9 => temp <= "0000100"; -- 9 
    end case;
    return temp;
end decod;
函数decod(x:在0到9的整数范围内)
返回标准逻辑向量为
变量温度:标准逻辑向量(6到0);
开始
案例x是

当0=>temp时,从变量声明中删除“in”关键字。也不必在函数参数列表中指定“in”,因为函数只接受“in”参数。您只需要指定端口和过程的方向。

除了Kevin的回答,您应该删除变量声明中的模式,因为您使用了错误的赋值类型
temp,去掉整数上的范围。如果要约束它(用于合成),请在函数外部创建一个整数子类型,或切换到
无符号
类型。
library ieee;
use ieee.std_logic_1164.all;

entity foo is
end entity;

architecture fum of foo is
    function decod ( x : in integer range 0 to 9)
return STD_LOGIC_VECTOR is 
variable temp : STD_LOGIC_VECTOR (6 downto 0);
    begin
    case x is
        when 0 => temp := "0000001"; -- 0
        when 1 => temp := "1001111"; -- 1
        when 2 => temp := "0010010"; -- 2
        when 3 => temp := "0000110"; -- 3 
        when 4 => temp := "1001100"; -- 4
        when 5 => temp := "0100100"; -- 5
        when 6 => temp := "0100000"; -- 6
        when 7 => temp := "0001111"; -- 7
        when 8 => temp := "0000000"; -- 8 
        when 9 => temp := "0000100"; -- 9 
    end case;
    return temp;
end decod;
begin
end architecture;
library ieee;
use ieee.std_logic_1164.all;


package fum is
    function decod ( x : in integer range 0 to 9) return STD_LOGIC_VECTOR;
end package fum;

package body fum is

    function decod ( x : in integer range 0 to 9) return STD_LOGIC_VECTOR is 
        variable temp : STD_LOGIC_VECTOR (6 downto 0);
    begin
        case x is
            when 0 => temp := "0000001"; -- 0
            when 1 => temp := "1001111"; -- 1
            when 2 => temp := "0010010"; -- 2
            when 3 => temp := "0000110"; -- 3 
            when 4 => temp := "1001100"; -- 4
            when 5 => temp := "0100100"; -- 5
            when 6 => temp := "0100000"; -- 6
            when 7 => temp := "0001111"; -- 7
            when 8 => temp := "0000000"; -- 8 
            when 9 => temp := "0000100"; -- 9 
        end case;
        return temp;
    end decod;
end package body;